diff --git a/arch/powerpc/include/asm/4xx_pci.h b/arch/powerpc/include/asm/4xx_pci.h
deleted file mode 100644
index 276a780..0000000
--- a/arch/powerpc/include/asm/4xx_pci.h
+++ /dev/null
@@ -1,62 +0,0 @@
-#ifndef _405GP_PCI_H
-#define _405GP_PCI_H
-
-#include <pci.h>
-
-/*----------------------------------------------------------------------------+
-| 405GP PCI core memory map defines.
-+----------------------------------------------------------------------------*/
-#define MIN_PCI_MEMADDR1    0x80000000
-#define MIN_PCI_MEMADDR2    0x00000000
-#define MIN_PLB_PCI_IOADDR  0xE8000000  /* PLB side of PCI I/O address space */
-#define MIN_PCI_PCI_IOADDR  0x00000000  /* PCI side of PCI I/O address space */
-#define MAX_PCI_DEVICES     32
-
-/*----------------------------------------------------------------------------+
-| Defines for the 405GP PCI Config address and data registers followed by
-| defines for the standard PCI device configuration header.
-+----------------------------------------------------------------------------*/
-#define PCICFGADR       0xEEC00000
-#define PCICFGDATA      0xEEC00004
-
-#define PCIBUSNUM       0x40        /* 405GP specific parameters */
-#define PCISUBBUSNUM    0x41
-#define PCIDISCOUNT     0x42
-#define PCIBRDGOPT1     0x4A
-#define PCIBRDGOPT2     0x60
-
-/*----------------------------------------------------------------------------+
-| Defines for 405GP PCI Master local configuration regs.
-+----------------------------------------------------------------------------*/
-#define PMM0LA          0xEF400000
-#define PMM0MA          0xEF400004
-#define PMM0PCILA       0xEF400008
-#define PMM0PCIHA       0xEF40000C
-#define PMM1LA          0xEF400010
-#define PMM1MA          0xEF400014
-#define PMM1PCILA       0xEF400018
-#define PMM1PCIHA       0xEF40001C
-#define PMM2LA          0xEF400020
-#define PMM2MA          0xEF400024
-#define PMM2PCILA       0xEF400028
-#define PMM2PCIHA       0xEF40002C
-
-/*----------------------------------------------------------------------------+
-| Defines for 405GP PCI Target local configuration regs.
-+----------------------------------------------------------------------------*/
-#define PTM1MS          0xEF400030
-#define PTM1LA          0xEF400034
-#define PTM2MS          0xEF400038
-#define PTM2LA          0xEF40003C
-
-#define PCIDEVID_405GP	0x0
-
-void board_pci_fixup_irq(struct pci_controller *hose, pci_dev_t dev);
-int pci_arbiter_enabled(void);
-int __pci_pre_init(struct pci_controller *hose);
-void __pci_target_init(struct pci_controller *hose);
-void __pci_master_init(struct pci_controller *hose);
-void pci_target_init(struct pci_controller *);
-void pcie_setup_hoses(int busno);
-
-#endif
diff --git a/arch/powerpc/include/asm/4xx_pcie.h b/arch/powerpc/include/asm/4xx_pcie.h
deleted file mode 100644
index 26b532a..0000000
--- a/arch/powerpc/include/asm/4xx_pcie.h
+++ /dev/null
@@ -1,406 +0,0 @@
-/*
- * Copyright (c) 2005 Cisco Systems.  All rights reserved.
- * Roland Dreier <rolandd@cisco.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef __4XX_PCIE_H
-#define __4XX_PCIE_H
-
-#include <asm/ppc4xx.h>
-#include <pci.h>
-
-#define DCRN_SDR0_CFGADDR	0x00e
-#define DCRN_SDR0_CFGDATA	0x00f
-
-#if defined(CONFIG_440SPE)
-#define CONFIG_SYS_PCIE_NR_PORTS	3
-
-#define CONFIG_SYS_PCIE_ADDR_HIGH	0x0000000d
-
-#define DCRN_PCIE0_BASE		0x100
-#define DCRN_PCIE1_BASE		0x120
-#define DCRN_PCIE2_BASE		0x140
-
-#define PCIE0_SDR		0x300
-#define PCIE1_SDR		0x340
-#define PCIE2_SDR		0x370
-#endif
-
-#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
-#define CONFIG_SYS_PCIE_NR_PORTS	2
-
-#define CONFIG_SYS_PCIE_ADDR_HIGH	0x0000000d
-
-#define DCRN_PCIE0_BASE		0x100
-#define DCRN_PCIE1_BASE		0x120
-
-#define PCIE0_SDR		0x300
-#define PCIE1_SDR		0x340
-#endif
-
-#if defined(CONFIG_405EX)
-#define CONFIG_SYS_PCIE_NR_PORTS	2
-
-#define CONFIG_SYS_PCIE_ADDR_HIGH	0x00000000
-
-#define	DCRN_PCIE0_BASE		0x040
-#define	DCRN_PCIE1_BASE		0x060
-
-#define PCIE0_SDR		0x400
-#define PCIE1_SDR		0x440
-#endif
-
-#define PCIE0			DCRN_PCIE0_BASE
-#define PCIE1			DCRN_PCIE1_BASE
-#define PCIE2			DCRN_PCIE2_BASE
-
-#define DCRN_PEGPL_CFGBAH(base)		(base + 0x00)
-#define DCRN_PEGPL_CFGBAL(base)		(base + 0x01)
-#define DCRN_PEGPL_CFGMSK(base)		(base + 0x02)
-#define DCRN_PEGPL_MSGBAH(base)		(base + 0x03)
-#define DCRN_PEGPL_MSGBAL(base)		(base + 0x04)
-#define DCRN_PEGPL_MSGMSK(base)		(base + 0x05)
-#define DCRN_PEGPL_OMR1BAH(base)	(base + 0x06)
-#define DCRN_PEGPL_OMR1BAL(base)	(base + 0x07)
-#define DCRN_PEGPL_OMR1MSKH(base)	(base + 0x08)
-#define DCRN_PEGPL_OMR1MSKL(base)	(base + 0x09)
-#define DCRN_PEGPL_REGBAH(base)		(base + 0x12)
-#define DCRN_PEGPL_REGBAL(base)		(base + 0x13)
-#define DCRN_PEGPL_REGMSK(base)		(base + 0x14)
-#define DCRN_PEGPL_SPECIAL(base)	(base + 0x15)
-#define DCRN_PEGPL_CFG(base)		(base + 0x16)
-
-/*
- * System DCRs (SDRs)
- */
-#define PESDR0_PLLLCT1		0x03a0
-#define PESDR0_PLLLCT2		0x03a1
-#define PESDR0_PLLLCT3		0x03a2
-
-/* common regs, at for all 4xx with PCIe core */
-#define SDRN_PESDR_UTLSET1(n)		(sdr_base(n) + 0x00)
-#define SDRN_PESDR_UTLSET2(n)		(sdr_base(n) + 0x01)
-#define SDRN_PESDR_DLPSET(n)		(sdr_base(n) + 0x02)
-#define SDRN_PESDR_LOOP(n)		(sdr_base(n) + 0x03)
-#define SDRN_PESDR_RCSSET(n)		(sdr_base(n) + 0x04)
-#define SDRN_PESDR_RCSSTS(n)		(sdr_base(n) + 0x05)
-
-#if defined(CONFIG_440SPE)
-#define SDRN_PESDR_HSSL0SET1(n)		(sdr_base(n) + 0x06)
-#define SDRN_PESDR_HSSL0SET2(n)		(sdr_base(n) + 0x07)
-#define SDRN_PESDR_HSSL0STS(n)		(sdr_base(n) + 0x08)
-#define SDRN_PESDR_HSSL1SET1(n)		(sdr_base(n) + 0x09)
-#define SDRN_PESDR_HSSL1SET2(n)		(sdr_base(n) + 0x0a)
-#define SDRN_PESDR_HSSL1STS(n)		(sdr_base(n) + 0x0b)
-#define SDRN_PESDR_HSSL2SET1(n)		(sdr_base(n) + 0x0c)
-#define SDRN_PESDR_HSSL2SET2(n)		(sdr_base(n) + 0x0d)
-#define SDRN_PESDR_HSSL2STS(n)		(sdr_base(n) + 0x0e)
-#define SDRN_PESDR_HSSL3SET1(n)		(sdr_base(n) + 0x0f)
-#define SDRN_PESDR_HSSL3SET2(n)		(sdr_base(n) + 0x10)
-#define SDRN_PESDR_HSSL3STS(n)		(sdr_base(n) + 0x11)
-
-#define PESDR0_UTLSET1		0x0300
-#define PESDR0_UTLSET2		0x0301
-#define PESDR0_DLPSET		0x0302
-#define PESDR0_LOOP		0x0303
-#define PESDR0_RCSSET		0x0304
-#define PESDR0_RCSSTS		0x0305
-#define PESDR0_HSSL0SET1	0x0306
-#define PESDR0_HSSL0SET2	0x0307
-#define PESDR0_HSSL0STS		0x0308
-#define PESDR0_HSSL1SET1	0x0309
-#define PESDR0_HSSL1SET2	0x030a
-#define PESDR0_HSSL1STS		0x030b
-#define PESDR0_HSSL2SET1	0x030c
-#define PESDR0_HSSL2SET2	0x030d
-#define PESDR0_HSSL2STS		0x030e
-#define PESDR0_HSSL3SET1	0x030f
-#define PESDR0_HSSL3SET2	0x0310
-#define PESDR0_HSSL3STS		0x0311
-#define PESDR0_HSSL4SET1	0x0312
-#define PESDR0_HSSL4SET2	0x0313
-#define PESDR0_HSSL4STS		0x0314
-#define PESDR0_HSSL5SET1	0x0315
-#define PESDR0_HSSL5SET2	0x0316
-#define PESDR0_HSSL5STS		0x0317
-#define PESDR0_HSSL6SET1	0x0318
-#define PESDR0_HSSL6SET2	0x0319
-#define PESDR0_HSSL6STS		0x031a
-#define PESDR0_HSSL7SET1	0x031b
-#define PESDR0_HSSL7SET2	0x031c
-#define PESDR0_HSSL7STS		0x031d
-#define PESDR0_HSSCTLSET	0x031e
-#define PESDR0_LANE_ABCD	0x031f
-#define PESDR0_LANE_EFGH	0x0320
-
-#define PESDR1_UTLSET1		0x0340
-#define PESDR1_UTLSET2		0x0341
-#define PESDR1_DLPSET		0x0342
-#define PESDR1_LOOP		0x0343
-#define PESDR1_RCSSET		0x0344
-#define PESDR1_RCSSTS		0x0345
-#define PESDR1_HSSL0SET1	0x0346
-#define PESDR1_HSSL0SET2	0x0347
-#define PESDR1_HSSL0STS		0x0348
-#define PESDR1_HSSL1SET1	0x0349
-#define PESDR1_HSSL1SET2	0x034a
-#define PESDR1_HSSL1STS		0x034b
-#define PESDR1_HSSL2SET1	0x034c
-#define PESDR1_HSSL2SET2	0x034d
-#define PESDR1_HSSL2STS		0x034e
-#define PESDR1_HSSL3SET1	0x034f
-#define PESDR1_HSSL3SET2	0x0350
-#define PESDR1_HSSL3STS		0x0351
-#define PESDR1_HSSCTLSET	0x0352
-#define PESDR1_LANE_ABCD	0x0353
-
-#define PESDR2_UTLSET1		0x0370
-#define PESDR2_UTLSET2		0x0371
-#define PESDR2_DLPSET		0x0372
-#define PESDR2_LOOP		0x0373
-#define PESDR2_RCSSET		0x0374
-#define PESDR2_RCSSTS		0x0375
-#define PESDR2_HSSL0SET1	0x0376
-#define PESDR2_HSSL0SET2	0x0377
-#define PESDR2_HSSL0STS		0x0378
-#define PESDR2_HSSL1SET1	0x0379
-#define PESDR2_HSSL1SET2	0x037a
-#define PESDR2_HSSL1STS		0x037b
-#define PESDR2_HSSL2SET1	0x037c
-#define PESDR2_HSSL2SET2	0x037d
-#define PESDR2_HSSL2STS		0x037e
-#define PESDR2_HSSL3SET1	0x037f
-#define PESDR2_HSSL3SET2	0x0380
-#define PESDR2_HSSL3STS		0x0381
-#define PESDR2_HSSCTLSET	0x0382
-#define PESDR2_LANE_ABCD	0x0383
-
-#elif defined(CONFIG_405EX)
-
-#define SDRN_PESDR_PHYSET1(n)		(sdr_base(n) + 0x06)
-#define SDRN_PESDR_PHYSET2(n)		(sdr_base(n) + 0x07)
-#define SDRN_PESDR_BIST(n)		(sdr_base(n) + 0x08)
-#define SDRN_PESDR_LPB(n)		(sdr_base(n) + 0x0b)
-#define SDRN_PESDR_PHYSTA(n)		(sdr_base(n) + 0x0c)
-
-#define PESDR0_UTLSET1		0x0400
-#define PESDR0_UTLSET2		0x0401
-#define PESDR0_DLPSET		0x0402
-#define PESDR0_LOOP		0x0403
-#define PESDR0_RCSSET		0x0404
-#define PESDR0_RCSSTS		0x0405
-#define PESDR0_PHYSET1		0x0406
-#define PESDR0_PHYSET2		0x0407
-#define PESDR0_BIST		0x0408
-#define PESDR0_LPB		0x040B
-#define PESDR0_PHYSTA		0x040C
-
-#define PESDR1_UTLSET1		0x0440
-#define PESDR1_UTLSET2		0x0441
-#define PESDR1_DLPSET		0x0442
-#define PESDR1_LOOP		0x0443
-#define PESDR1_RCSSET		0x0444
-#define PESDR1_RCSSTS		0x0445
-#define PESDR1_PHYSET1		0x0446
-#define PESDR1_PHYSET2		0x0447
-#define PESDR1_BIST		0x0448
-#define PESDR1_LPB		0x044B
-#define PESDR1_PHYSTA		0x044C
-
-#elif defined(CONFIG_460EX) || defined(CONFIG_460GT)
-
-#define PESDR0_L0BIST		0x0308	/* PE0 L0 built in self test */
-#define PESDR0_L0BISTSTS	0x0309	/* PE0 L0 built in self test status */
-#define PESDR0_L0CDRCTL		0x030A	/* PE0 L0 CDR control */
-#define PESDR0_L0DRV		0x030B	/* PE0 L0 drive */
-#define PESDR0_L0REC		0x030C	/* PE0 L0 receiver */
-#define PESDR0_L0LPB		0x030D	/* PE0 L0 loopback */
-#define PESDR0_L0CLK		0x030E	/* PE0 L0 clocking */
-#define PESDR0_PHY_CTL_RST	0x030F	/* PE0 PHY control reset */
-#define PESDR0_RSTSTA		0x0310	/* PE0 reset status */
-#define PESDR0_OBS		0x0311	/* PE0 observation register */
-#define PESDR0_L0ERRC		0x0320	/* PE0 L0 error counter */
-
-#define PESDR1_L0BIST		0x0348	/* PE1 L0 built in self test */
-#define PESDR1_L1BIST		0x0349	/* PE1 L1 built in self test */
-#define PESDR1_L2BIST		0x034A	/* PE1 L2 built in self test */
-#define PESDR1_L3BIST		0x034B	/* PE1 L3 built in self test */
-#define PESDR1_L0BISTSTS	0x034C	/* PE1 L0 built in self test status */
-#define PESDR1_L1BISTSTS	0x034D	/* PE1 L1 built in self test status */
-#define PESDR1_L2BISTSTS	0x034E	/* PE1 L2 built in self test status */
-#define PESDR1_L3BISTSTS	0x034F	/* PE1 L3 built in self test status */
-#define PESDR1_L0CDRCTL		0x0350	/* PE1 L0 CDR control */
-#define PESDR1_L1CDRCTL		0x0351	/* PE1 L1 CDR control */
-#define PESDR1_L2CDRCTL		0x0352	/* PE1 L2 CDR control */
-#define PESDR1_L3CDRCTL		0x0353	/* PE1 L3 CDR control */
-#define PESDR1_L0DRV		0x0354	/* PE1 L0 drive */
-#define PESDR1_L1DRV		0x0355	/* PE1 L1 drive */
-#define PESDR1_L2DRV		0x0356	/* PE1 L2 drive */
-#define PESDR1_L3DRV		0x0357	/* PE1 L3 drive */
-#define PESDR1_L0REC		0x0358	/* PE1 L0 receiver */
-#define PESDR1_L1REC		0x0359	/* PE1 L1 receiver */
-#define PESDR1_L2REC		0x035A	/* PE1 L2 receiver */
-#define PESDR1_L3REC		0x035B	/* PE1 L3 receiver */
-#define PESDR1_L0LPB		0x035C	/* PE1 L0 loopback */
-#define PESDR1_L1LPB		0x035D	/* PE1 L1 loopback */
-#define PESDR1_L2LPB		0x035E	/* PE1 L2 loopback */
-#define PESDR1_L3LPB		0x035F	/* PE1 L3 loopback */
-#define PESDR1_L0CLK		0x0360	/* PE1 L0 clocking */
-#define PESDR1_L1CLK		0x0361	/* PE1 L1 clocking */
-#define PESDR1_L2CLK		0x0362	/* PE1 L2 clocking */
-#define PESDR1_L3CLK		0x0363	/* PE1 L3 clocking */
-#define PESDR1_PHY_CTL_RST	0x0364	/* PE1 PHY control reset */
-#define PESDR1_RSTSTA		0x0365	/* PE1 reset status */
-#define PESDR1_OBS		0x0366	/* PE1 observation register */
-#define PESDR1_L0ERRC		0x0368	/* PE1 L0 error counter */
-#define PESDR1_L1ERRC		0x0369	/* PE1 L1 error counter */
-#define PESDR1_L2ERRC		0x036A	/* PE1 L2 error counter */
-#define PESDR1_L3ERRC		0x036B	/* PE1 L3 error counter */
-#define PESDR0_IHS1		0x036C	/* PE interrupt handler interfact setting 1 */
-#define PESDR0_IHS2		0x036D	/* PE interrupt handler interfact setting 2 */
-
-#endif
-
-/* SDR Bit Mappings */
-#define PESDRx_RCSSET_HLDPLB	0x10000000
-#define PESDRx_RCSSET_RSTGU	0x01000000
-#define PESDRx_RCSSET_RDY       0x00100000
-#define PESDRx_RCSSET_RSTDL     0x00010000
-#define PESDRx_RCSSET_RSTPYN    0x00001000
-
-#define PESDRx_RCSSTS_PLBIDL	0x10000000
-#define PESDRx_RCSSTS_HRSTRQ	0x01000000
-#define PESDRx_RCSSTS_PGRST	0x00100000
-#define PESDRx_RCSSTS_VC0ACT	0x00010000
-#define PESDRx_RCSSTS_BMEN	0x00000100
-
-/*
- * UTL register offsets
- */
-#define	PEUTL_PBCTL		0x00
-#define PEUTL_PBBSZ		0x20
-#define PEUTL_OPDBSZ		0x68
-#define PEUTL_IPHBSZ		0x70
-#define PEUTL_IPDBSZ		0x78
-#define PEUTL_OUTTR		0x90
-#define PEUTL_INTR		0x98
-#define PEUTL_PCTL		0xa0
-#define	PEUTL_RCSTA		0xb0
-#define PEUTL_RCIRQEN		0xb8
-
-/*
- * Config space register offsets
- */
-#define PECFG_BAR0LMPA		0x210
-#define PECFG_BAR0HMPA		0x214
-#define PECFG_BAR1MPA		0x218
-#define PECFG_BAR2LMPA		0x220
-#define PECFG_BAR2HMPA		0x224
-
-#define PECFG_PIMEN		0x33c
-#define PECFG_PIM0LAL		0x340
-#define PECFG_PIM0LAH		0x344
-#define PECFG_PIM1LAL		0x348
-#define PECFG_PIM1LAH		0x34c
-#define PECFG_PIM01SAL		0x350
-#define PECFG_PIM01SAH		0x354
-
-#define PECFG_POM0LAL		0x380
-#define PECFG_POM0LAH		0x384
-
-#define SDR_READ(offset) ({\
-	mtdcr(DCRN_SDR0_CFGADDR, offset); \
-	mfdcr(DCRN_SDR0_CFGDATA);})
-
-#define SDR_WRITE(offset, data) ({\
-	mtdcr(DCRN_SDR0_CFGADDR, offset); \
-	mtdcr(DCRN_SDR0_CFGDATA,data);})
-
-#define GPL_DMER_MASK_DISA	0x02000000
-
-#define U64_TO_U32_LOW(val)	((u32)((val) & 0x00000000ffffffffULL))
-#define U64_TO_U32_HIGH(val)	((u32)((val) >> 32))
-
-/*
- * Prototypes
- */
-int ppc4xx_init_pcie(void);
-int ppc4xx_init_pcie_rootport(int port);
-int ppc4xx_init_pcie_endport(int port);
-void ppc4xx_setup_pcie_rootpoint(struct pci_controller *hose, int port);
-int ppc4xx_setup_pcie_endpoint(struct pci_controller *hose, int port);
-int pcie_hose_scan(struct pci_controller *hose, int bus);
-
-/*
- * Function to determine root port or endport from env variable.
- */
-static inline int is_end_point(int port)
-{
-	char s[10], *tk;
-	char *pcie_mode = getenv("pcie_mode");
-
-	if (pcie_mode == NULL)
-		return 0;
-
-	strcpy(s, pcie_mode);
-	tk = strtok(s, ":");
-
-	switch (port) {
-	case 0:
-		if (tk != NULL) {
-			if (!(strcmp(tk, "ep") && strcmp(tk, "EP")))
-				return 1;
-			else
-				return 0;
-		}
-		else
-			return 0;
-
-	case 1:
-		tk = strtok(NULL, ":");
-		if (tk != NULL) {
-			if (!(strcmp(tk, "ep") && strcmp(tk, "EP")))
-				return 1;
-			else
-				return 0;
-		}
-		else
-			return 0;
-
-	case 2:
-		tk = strtok(NULL, ":");
-		if (tk != NULL)
-			tk = strtok(NULL, ":");
-		if (tk != NULL) {
-			if (!(strcmp(tk, "ep") && strcmp(tk, "EP")))
-				return 1;
-			else
-				return 0;
-		}
-		else
-			return 0;
-	}
-
-	return 0;
-}
-
-#if defined(PCIE0_SDR)
-static inline u32 sdr_base(int port)
-{
-	switch (port) {
-	default:	/* to satisfy compiler */
-	case 0:
-		return PCIE0_SDR;
-	case 1:
-		return PCIE1_SDR;
-#if CONFIG_SYS_PCIE_NR_PORTS > 2
-	case 2:
-		return PCIE2_SDR;
-#endif
-	}
-}
-#endif /* defined(PCIE0_SDR) */
-
-#endif /* __4XX_PCIE_H */
diff --git a/arch/powerpc/include/asm/config.h b/arch/powerpc/include/asm/config.h
index 55686a1..eaa23d2 100644
--- a/arch/powerpc/include/asm/config.h
+++ b/arch/powerpc/include/asm/config.h
@@ -35,8 +35,7 @@
 #define CONFIG_SYS_BOOT_GET_KBD
 
 #ifndef CONFIG_MAX_MEM_MAPPED
-#if	defined(CONFIG_4xx)		|| \
-	defined(CONFIG_E500)		|| \
+#if	defined(CONFIG_E500)		|| \
 	defined(CONFIG_MPC86xx)		|| \
 	defined(CONFIG_E300)
 #define CONFIG_MAX_MEM_MAPPED	((phys_size_t)2 << 30)
diff --git a/arch/powerpc/include/asm/global_data.h b/arch/powerpc/include/asm/global_data.h
index d0c3fa0..1c4a82c 100644
--- a/arch/powerpc/include/asm/global_data.h
+++ b/arch/powerpc/include/asm/global_data.h
@@ -90,9 +90,6 @@
 	unsigned int dp_alloc_base;
 	unsigned int dp_alloc_top;
 #endif
-#if defined(CONFIG_4xx)
-	u32 uart_clk;
-#endif /* CONFIG_4xx */
 #ifdef CONFIG_SYS_FPGA_COUNT
 	unsigned fpga_state[CONFIG_SYS_FPGA_COUNT];
 #endif
diff --git a/arch/powerpc/include/asm/interrupt.h b/arch/powerpc/include/asm/interrupt.h
index 9f370dd..c039fc5 100644
--- a/arch/powerpc/include/asm/interrupt.h
+++ b/arch/powerpc/include/asm/interrupt.h
@@ -9,17 +9,6 @@
 #ifndef INTERRUPT_H
 #define INTERRUPT_H
 
-#if defined(CONFIG_XILINX_440)
-#include <asm/xilinx_irq.h>
-#else
-#include <asm/ppc4xx-uic.h>
-#endif
-
-void pic_enable(void);
-void pic_irq_enable(unsigned int irq);
-void pic_irq_disable(unsigned int irq);
-void pic_irq_ack(unsigned int irq);
 void external_interrupt(struct pt_regs *regs);
-void interrupt_run_handler(int vec);
 
 #endif
diff --git a/arch/powerpc/include/asm/mmu.h b/arch/powerpc/include/asm/mmu.h
index 5aa916f..82e5f9f 100644
--- a/arch/powerpc/include/asm/mmu.h
+++ b/arch/powerpc/include/asm/mmu.h
@@ -585,213 +585,4 @@
 #define LAWAR_SIZE_32G		(LAWAR_SIZE_BASE+24)
 #endif
 
-#ifdef CONFIG_440
-/* General */
-#define TLB_VALID   0x00000200
-
-/* Supported page sizes */
-
-#define SZ_1K	0x00000000
-#define SZ_4K	0x00000010
-#define SZ_16K	0x00000020
-#define SZ_64K	0x00000030
-#define SZ_256K	0x00000040
-#define SZ_1M	0x00000050
-#define SZ_16M	0x00000070
-#define SZ_256M	0x00000090
-
-/* Storage attributes */
-#define SA_W	0x00000800	/* Write-through */
-#define SA_I	0x00000400	/* Caching inhibited */
-#define SA_M	0x00000200	/* Memory coherence */
-#define SA_G	0x00000100	/* Guarded */
-#define SA_E	0x00000080	/* Endian */
-/* Some additional macros for combinations often used */
-#define SA_IG	(SA_I | SA_G)
-
-/* Access control */
-#define AC_X	0x00000024	/* Execute */
-#define AC_W	0x00000012	/* Write */
-#define AC_R	0x00000009	/* Read */
-/* Some additional macros for combinations often used */
-#define AC_RW	(AC_R | AC_W)
-#define AC_RWX	(AC_R | AC_W | AC_X)
-
-/* Some handy macros */
-
-#define EPN(e)		((e) & 0xfffffc00)
-#define TLB0(epn,sz)	((EPN((epn)) | (sz) | TLB_VALID ))
-#define TLB1(rpn,erpn)	(((rpn) & 0xfffffc00) | (erpn))
-#define TLB2(a)		((a) & 0x00000fbf)
-
-#define tlbtab_start\
-	mflr	r1	;\
-	bl	0f	;
-
-#define tlbtab_end\
-	.long 0, 0, 0	;\
-0:	mflr	r0	;\
-	mtlr	r1	;\
-	blr		;
-
-#define tlbentry(epn,sz,rpn,erpn,attr)\
-	.long TLB0(epn,sz),TLB1(rpn,erpn),TLB2(attr)
-
-/*----------------------------------------------------------------------------+
-| TLB specific defines.
-+----------------------------------------------------------------------------*/
-#define TLB_256MB_ALIGN_MASK 0xFF0000000ULL
-#define TLB_16MB_ALIGN_MASK  0xFFF000000ULL
-#define TLB_1MB_ALIGN_MASK   0xFFFF00000ULL
-#define TLB_256KB_ALIGN_MASK 0xFFFFC0000ULL
-#define TLB_64KB_ALIGN_MASK  0xFFFFF0000ULL
-#define TLB_16KB_ALIGN_MASK  0xFFFFFC000ULL
-#define TLB_4KB_ALIGN_MASK   0xFFFFFF000ULL
-#define TLB_1KB_ALIGN_MASK   0xFFFFFFC00ULL
-#define TLB_256MB_SIZE       0x10000000
-#define TLB_16MB_SIZE        0x01000000
-#define TLB_1MB_SIZE         0x00100000
-#define TLB_256KB_SIZE       0x00040000
-#define TLB_64KB_SIZE        0x00010000
-#define TLB_16KB_SIZE        0x00004000
-#define TLB_4KB_SIZE         0x00001000
-#define TLB_1KB_SIZE         0x00000400
-
-#define TLB_WORD0_EPN_MASK   0xFFFFFC00
-#define TLB_WORD0_EPN_ENCODE(n) (((unsigned long)(n))&0xFFFFFC00)
-#define TLB_WORD0_EPN_DECODE(n) (((unsigned long)(n))&0xFFFFFC00)
-#define TLB_WORD0_V_MASK     0x00000200
-#define TLB_WORD0_V_ENABLE   0x00000200
-#define TLB_WORD0_V_DISABLE  0x00000000
-#define TLB_WORD0_TS_MASK    0x00000100
-#define TLB_WORD0_TS_1       0x00000100
-#define TLB_WORD0_TS_0       0x00000000
-#define TLB_WORD0_SIZE_MASK  0x000000F0
-#define TLB_WORD0_SIZE_1KB   0x00000000
-#define TLB_WORD0_SIZE_4KB   0x00000010
-#define TLB_WORD0_SIZE_16KB  0x00000020
-#define TLB_WORD0_SIZE_64KB  0x00000030
-#define TLB_WORD0_SIZE_256KB 0x00000040
-#define TLB_WORD0_SIZE_1MB   0x00000050
-#define TLB_WORD0_SIZE_16MB  0x00000070
-#define TLB_WORD0_SIZE_256MB 0x00000090
-#define TLB_WORD0_TPAR_MASK  0x0000000F
-#define TLB_WORD0_TPAR_ENCODE(n) ((((unsigned long)(n))&0x0F)<<0)
-#define TLB_WORD0_TPAR_DECODE(n) ((((unsigned long)(n))>>0)&0x0F)
-
-#define TLB_WORD1_RPN_MASK   0xFFFFFC00
-#define TLB_WORD1_RPN_ENCODE(n) (((unsigned long)(n))&0xFFFFFC00)
-#define TLB_WORD1_RPN_DECODE(n) (((unsigned long)(n))&0xFFFFFC00)
-#define TLB_WORD1_PAR1_MASK  0x00000300
-#define TLB_WORD1_PAR1_ENCODE(n) ((((unsigned long)(n))&0x03)<<8)
-#define TLB_WORD1_PAR1_DECODE(n) ((((unsigned long)(n))>>8)&0x03)
-#define TLB_WORD1_PAR1_0     0x00000000
-#define TLB_WORD1_PAR1_1     0x00000100
-#define TLB_WORD1_PAR1_2     0x00000200
-#define TLB_WORD1_PAR1_3     0x00000300
-#define TLB_WORD1_ERPN_MASK  0x0000000F
-#define TLB_WORD1_ERPN_ENCODE(n) ((((unsigned long)(n))&0x0F)<<0)
-#define TLB_WORD1_ERPN_DECODE(n) ((((unsigned long)(n))>>0)&0x0F)
-
-#define TLB_WORD2_PAR2_MASK  0xC0000000
-#define TLB_WORD2_PAR2_ENCODE(n) ((((unsigned long)(n))&0x03)<<30)
-#define TLB_WORD2_PAR2_DECODE(n) ((((unsigned long)(n))>>30)&0x03)
-#define TLB_WORD2_PAR2_0     0x00000000
-#define TLB_WORD2_PAR2_1     0x40000000
-#define TLB_WORD2_PAR2_2     0x80000000
-#define TLB_WORD2_PAR2_3     0xC0000000
-#define TLB_WORD2_U0_MASK    0x00008000
-#define TLB_WORD2_U0_ENABLE  0x00008000
-#define TLB_WORD2_U0_DISABLE 0x00000000
-#define TLB_WORD2_U1_MASK    0x00004000
-#define TLB_WORD2_U1_ENABLE  0x00004000
-#define TLB_WORD2_U1_DISABLE 0x00000000
-#define TLB_WORD2_U2_MASK    0x00002000
-#define TLB_WORD2_U2_ENABLE  0x00002000
-#define TLB_WORD2_U2_DISABLE 0x00000000
-#define TLB_WORD2_U3_MASK    0x00001000
-#define TLB_WORD2_U3_ENABLE  0x00001000
-#define TLB_WORD2_U3_DISABLE 0x00000000
-#define TLB_WORD2_W_MASK     0x00000800
-#define TLB_WORD2_W_ENABLE   0x00000800
-#define TLB_WORD2_W_DISABLE  0x00000000
-#define TLB_WORD2_I_MASK     0x00000400
-#define TLB_WORD2_I_ENABLE   0x00000400
-#define TLB_WORD2_I_DISABLE  0x00000000
-#define TLB_WORD2_M_MASK     0x00000200
-#define TLB_WORD2_M_ENABLE   0x00000200
-#define TLB_WORD2_M_DISABLE  0x00000000
-#define TLB_WORD2_G_MASK     0x00000100
-#define TLB_WORD2_G_ENABLE   0x00000100
-#define TLB_WORD2_G_DISABLE  0x00000000
-#define TLB_WORD2_E_MASK     0x00000080
-#define TLB_WORD2_E_ENABLE   0x00000080
-#define TLB_WORD2_E_DISABLE  0x00000000
-#define TLB_WORD2_UX_MASK    0x00000020
-#define TLB_WORD2_UX_ENABLE  0x00000020
-#define TLB_WORD2_UX_DISABLE 0x00000000
-#define TLB_WORD2_UW_MASK    0x00000010
-#define TLB_WORD2_UW_ENABLE  0x00000010
-#define TLB_WORD2_UW_DISABLE 0x00000000
-#define TLB_WORD2_UR_MASK    0x00000008
-#define TLB_WORD2_UR_ENABLE  0x00000008
-#define TLB_WORD2_UR_DISABLE 0x00000000
-#define TLB_WORD2_SX_MASK    0x00000004
-#define TLB_WORD2_SX_ENABLE  0x00000004
-#define TLB_WORD2_SX_DISABLE 0x00000000
-#define TLB_WORD2_SW_MASK    0x00000002
-#define TLB_WORD2_SW_ENABLE  0x00000002
-#define TLB_WORD2_SW_DISABLE 0x00000000
-#define TLB_WORD2_SR_MASK    0x00000001
-#define TLB_WORD2_SR_ENABLE  0x00000001
-#define TLB_WORD2_SR_DISABLE 0x00000000
-
-/*----------------------------------------------------------------------------+
-| Following instructions are not available in Book E mode of the GNU assembler.
-+----------------------------------------------------------------------------*/
-#define DCCCI(ra,rb)			.long 0x7c000000|\
-					(ra<<16)|(rb<<11)|(454<<1)
-
-#define ICCCI(ra,rb)			.long 0x7c000000|\
-					(ra<<16)|(rb<<11)|(966<<1)
-
-#define DCREAD(rt,ra,rb)		.long 0x7c000000|\
-					(rt<<21)|(ra<<16)|(rb<<11)|(486<<1)
-
-#define ICREAD(ra,rb)			.long 0x7c000000|\
-					(ra<<16)|(rb<<11)|(998<<1)
-
-#define TLBSX(rt,ra,rb)			.long 0x7c000000|\
-					(rt<<21)|(ra<<16)|(rb<<11)|(914<<1)
-
-#define TLBWE(rs,ra,ws)			.long 0x7c000000|\
-					(rs<<21)|(ra<<16)|(ws<<11)|(978<<1)
-
-#define TLBRE(rt,ra,ws)			.long 0x7c000000|\
-					(rt<<21)|(ra<<16)|(ws<<11)|(946<<1)
-
-#define TLBSXDOT(rt,ra,rb)		.long 0x7c000001|\
-					(rt<<21)|(ra<<16)|(rb<<11)|(914<<1)
-
-#define MSYNC				.long 0x7c000000|\
-					(598<<1)
-
-#define MBAR_INST				.long 0x7c000000|\
-					(854<<1)
-
-#ifndef __ASSEMBLY__
-/* Prototypes */
-void mttlb1(unsigned long index, unsigned long value);
-void mttlb2(unsigned long index, unsigned long value);
-void mttlb3(unsigned long index, unsigned long value);
-unsigned long mftlb1(unsigned long index);
-unsigned long mftlb2(unsigned long index);
-unsigned long mftlb3(unsigned long index);
-
-void program_tlb(u64 phys_addr, u32 virt_addr, u32 size, u32 tlb_word2_i_value);
-void remove_tlb(u32 vaddr, u32 size);
-void change_tlb(u32 vaddr, u32 size, u32 tlb_word2_i_value);
-#endif /* __ASSEMBLY__ */
-
-#endif /* CONFIG_440 */
 #endif /* _PPC_MMU_H_ */
diff --git a/arch/powerpc/include/asm/ppc.h b/arch/powerpc/include/asm/ppc.h
index 4d9af6c..aa6c304 100644
--- a/arch/powerpc/include/asm/ppc.h
+++ b/arch/powerpc/include/asm/ppc.h
@@ -25,9 +25,6 @@
 #include <mpc83xx.h>
 #include <asm/immap_83xx.h>
 #endif
-#ifdef	CONFIG_4xx
-#include <asm/ppc4xx.h>
-#endif
 #ifdef CONFIG_SOC_DA8XX
 #include <asm/arch/hardware.h>
 #endif
@@ -47,8 +44,7 @@
 void wr_dc_cst(uint);
 void wr_dc_adr(uint);
 
-#if defined(CONFIG_4xx)	|| \
-	defined(CONFIG_MPC85xx)	|| \
+#if defined(CONFIG_MPC85xx)	|| \
 	defined(CONFIG_MPC86xx)	|| \
 	defined(CONFIG_MPC83xx)
 unsigned char	in8(unsigned int);
diff --git a/arch/powerpc/include/asm/ppc405.h b/arch/powerpc/include/asm/ppc405.h
deleted file mode 100644
index f2ed16a..0000000
--- a/arch/powerpc/include/asm/ppc405.h
+++ /dev/null
@@ -1,57 +0,0 @@
-/*
- * SPDX-License-Identifier:	GPL-2.0	IBM-pibs
- */
-
-#ifndef	__PPC405_H__
-#define __PPC405_H__
-
-/* Define bits and masks for real-mode storage attribute control registers */
-#define PPC_128MB_SACR_BIT(addr)	((addr) >> 27)
-#define PPC_128MB_SACR_VALUE(addr)	PPC_REG_VAL(PPC_128MB_SACR_BIT(addr),1)
-
-#define CONFIG_SYS_DCACHE_SIZE		(16 << 10)	/* For AMCC 405 CPUs */
-
-/* DCR registers */
-#define PLB0_ACR	0x0087
-
-/* SDR registers */
-#define SDR0_PINSTP	0x0040
-
-/* CPR registers */
-#define CPR0_CLKUPD	0x0020
-#define CPR0_PLLC	0x0040
-#define CPR0_PLLD	0x0060
-#define CPR0_CPUD	0x0080
-#define CPR0_PLBD	0x00a0
-#define CPR0_OPBD0	0x00c0
-#define CPR0_PERD	0x00e0
-
-/*
- * DMA
- */
-#define DMA_DCR_BASE	0x0100
-#define DMACR0		(DMA_DCR_BASE + 0x00)  /* DMA channel control reg 0	*/
-#define DMACT0		(DMA_DCR_BASE + 0x01)  /* DMA count reg 0		*/
-#define DMADA0		(DMA_DCR_BASE + 0x02)  /* DMA destination address reg 0 */
-#define DMASA0		(DMA_DCR_BASE + 0x03)  /* DMA source address reg 0	*/
-#define DMASB0		(DMA_DCR_BASE + 0x04)  /* DMA sg descriptor addr 0	*/
-#define DMACR1		(DMA_DCR_BASE + 0x08)  /* DMA channel control reg 1	*/
-#define DMACT1		(DMA_DCR_BASE + 0x09)  /* DMA count reg 1		*/
-#define DMADA1		(DMA_DCR_BASE + 0x0a)  /* DMA destination address reg 1 */
-#define DMASA1		(DMA_DCR_BASE + 0x0b)  /* DMA source address reg 1	*/
-#define DMASB1		(DMA_DCR_BASE + 0x0c)  /* DMA sg descriptor addr 1	*/
-#define DMACR2		(DMA_DCR_BASE + 0x10)  /* DMA channel control reg 2	*/
-#define DMACT2		(DMA_DCR_BASE + 0x11)  /* DMA count reg 2		*/
-#define DMADA2		(DMA_DCR_BASE + 0x12)  /* DMA destination address reg 2 */
-#define DMASA2		(DMA_DCR_BASE + 0x13)  /* DMA source address reg 2	*/
-#define DMASB2		(DMA_DCR_BASE + 0x14)  /* DMA sg descriptor addr 2	*/
-#define DMACR3		(DMA_DCR_BASE + 0x18)  /* DMA channel control reg 3	*/
-#define DMACT3		(DMA_DCR_BASE + 0x19)  /* DMA count reg 3		*/
-#define DMADA3		(DMA_DCR_BASE + 0x1a)  /* DMA destination address reg 3 */
-#define DMASA3		(DMA_DCR_BASE + 0x1b)  /* DMA source address reg 3	*/
-#define DMASB3		(DMA_DCR_BASE + 0x1c)  /* DMA sg descriptor addr 3	*/
-#define DMASR		(DMA_DCR_BASE + 0x20)  /* DMA status reg		*/
-#define DMASGC		(DMA_DCR_BASE + 0x23)  /* DMA scatter/gather command reg*/
-#define DMAADR		(DMA_DCR_BASE + 0x24)  /* DMA address decode reg	*/
-
-#endif	/* __PPC405_H__ */
diff --git a/arch/powerpc/include/asm/ppc405ep.h b/arch/powerpc/include/asm/ppc405ep.h
deleted file mode 100644
index 9f04215..0000000
--- a/arch/powerpc/include/asm/ppc405ep.h
+++ /dev/null
@@ -1,239 +0,0 @@
-/*
- * (C) Copyright 2010
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef _PPC405EP_H_
-#define _PPC405EP_H_
-
-#define CONFIG_SDRAM_PPC4xx_IBM_SDRAM	/* IBM SDRAM controller */
-
-/* Memory mapped register */
-#define CONFIG_SYS_PERIPHERAL_BASE	0xef600000 /* Internal Peripherals */
-
-#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_PERIPHERAL_BASE + 0x0300)
-#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_PERIPHERAL_BASE + 0x0400)
-
-#define GPIO0_BASE		(CONFIG_SYS_PERIPHERAL_BASE + 0x0700)
-
-/* DCR */
-#define OCM0_ISCNTL	0x0019	/* OCM I-side control reg */
-#define OCM0_DSARC	0x001a	/* OCM D-side address compare */
-#define OCM0_DSCNTL	0x001b	/* OCM D-side control */
-#define CPC0_PLLMR0	0x00f0	/* PLL mode  register 0	*/
-#define CPC0_BOOT	0x00f1	/* Clock status register	*/
-#define CPC0_CR1	0x00f2	/* Chip Control 1 register */
-#define CPC0_EPCTL	0x00f3	/* EMAC to PHY control register */
-#define CPC0_PLLMR1	0x00f4	/* PLL mode  register 1	*/
-#define CPC0_UCR	0x00f5	/* UART control register	*/
-#define CPC0_SRR	0x00f6	/* Soft Reset register */
-#define CPC0_PCI	0x00f9	/* PCI control register	*/
-
-/* Defines for CPC0_EPCTL register */
-#define CPC0_EPCTL_E0NFE	0x80000000
-#define CPC0_EPCTL_E1NFE	0x40000000
-
-/* Defines for CPC0_PCI Register */
-#define CPC0_PCI_SPE		0x00000010	/* PCIINT/WE select	 */
-#define CPC0_PCI_HOST_CFG_EN	0x00000008	/* PCI host config Enable */
-#define CPC0_PCI_ARBIT_EN	0x00000001	/* PCI Internal Arb Enabled */
-
-/* Defines for CPC0_BOOR Register */
-#define CPC0_BOOT_SEP		0x00000002	/* serial EEPROM present */
-
-/* Bit definitions */
-#define PLLMR0_CPU_DIV_MASK	0x00300000	/* CPU clock divider */
-#define PLLMR0_CPU_DIV_BYPASS	0x00000000
-#define PLLMR0_CPU_DIV_2	0x00100000
-#define PLLMR0_CPU_DIV_3	0x00200000
-#define PLLMR0_CPU_DIV_4	0x00300000
-
-#define PLLMR0_CPU_TO_PLB_MASK	0x00030000	/* CPU:PLB Frequency Divisor */
-#define PLLMR0_CPU_PLB_DIV_1	0x00000000
-#define PLLMR0_CPU_PLB_DIV_2	0x00010000
-#define PLLMR0_CPU_PLB_DIV_3	0x00020000
-#define PLLMR0_CPU_PLB_DIV_4	0x00030000
-
-#define PLLMR0_OPB_TO_PLB_MASK	0x00003000	/* OPB:PLB Frequency Divisor */
-#define PLLMR0_OPB_PLB_DIV_1	0x00000000
-#define PLLMR0_OPB_PLB_DIV_2	0x00001000
-#define PLLMR0_OPB_PLB_DIV_3	0x00002000
-#define PLLMR0_OPB_PLB_DIV_4	0x00003000
-
-#define PLLMR0_EXB_TO_PLB_MASK	0x00000300	/* External Bus:PLB Divisor */
-#define PLLMR0_EXB_PLB_DIV_2	0x00000000
-#define PLLMR0_EXB_PLB_DIV_3	0x00000100
-#define PLLMR0_EXB_PLB_DIV_4	0x00000200
-#define PLLMR0_EXB_PLB_DIV_5	0x00000300
-
-#define PLLMR0_MAL_TO_PLB_MASK	0x00000030	/* MAL:PLB Divisor */
-#define PLLMR0_MAL_PLB_DIV_1	0x00000000
-#define PLLMR0_MAL_PLB_DIV_2	0x00000010
-#define PLLMR0_MAL_PLB_DIV_3	0x00000020
-#define PLLMR0_MAL_PLB_DIV_4	0x00000030
-
-#define PLLMR0_PCI_TO_PLB_MASK	0x00000003	/* PCI:PLB Frequency Divisor */
-#define PLLMR0_PCI_PLB_DIV_1	0x00000000
-#define PLLMR0_PCI_PLB_DIV_2	0x00000001
-#define PLLMR0_PCI_PLB_DIV_3	0x00000002
-#define PLLMR0_PCI_PLB_DIV_4	0x00000003
-
-#define PLLMR1_SSCS_MASK	0x80000000	/* Select system clock source */
-#define PLLMR1_PLLR_MASK	0x40000000	/* PLL reset */
-#define PLLMR1_FBMUL_MASK	0x00F00000	/* PLL feedback multiplier value */
-
-#define PLLMR1_FWDVA_MASK	0x00070000	/* PLL forward divider A value */
-#define PLLMR1_FWDVB_MASK	0x00007000	/* PLL forward divider B value */
-#define PLLMR1_TUNING_MASK	0x000003FF	/* PLL tune bits */
-
-/* Defines for CPC0_PLLMR1 Register fields */
-#define PLL_ACTIVE		0x80000000
-#define CPC0_PLLMR1_SSCS	0x80000000
-#define PLL_RESET		0x40000000
-#define CPC0_PLLMR1_PLLR	0x40000000
-/* Feedback multiplier */
-#define PLL_FBKDIV		0x00F00000
-#define CPC0_PLLMR1_FBDV	0x00F00000
-#define PLL_FBKDIV_16		0x00000000
-#define PLL_FBKDIV_1		0x00100000
-#define PLL_FBKDIV_2		0x00200000
-#define PLL_FBKDIV_3		0x00300000
-#define PLL_FBKDIV_4		0x00400000
-#define PLL_FBKDIV_5		0x00500000
-#define PLL_FBKDIV_6		0x00600000
-#define PLL_FBKDIV_7		0x00700000
-#define PLL_FBKDIV_8		0x00800000
-#define PLL_FBKDIV_9		0x00900000
-#define PLL_FBKDIV_10		0x00A00000
-#define PLL_FBKDIV_11		0x00B00000
-#define PLL_FBKDIV_12		0x00C00000
-#define PLL_FBKDIV_13		0x00D00000
-#define PLL_FBKDIV_14		0x00E00000
-#define PLL_FBKDIV_15		0x00F00000
-/* Forward A divisor */
-#define PLL_FWDDIVA		0x00070000
-#define CPC0_PLLMR1_FWDVA	0x00070000
-#define PLL_FWDDIVA_8		0x00000000
-#define PLL_FWDDIVA_7		0x00010000
-#define PLL_FWDDIVA_6		0x00020000
-#define PLL_FWDDIVA_5		0x00030000
-#define PLL_FWDDIVA_4		0x00040000
-#define PLL_FWDDIVA_3		0x00050000
-#define PLL_FWDDIVA_2		0x00060000
-#define PLL_FWDDIVA_1		0x00070000
-/* Forward B divisor */
-#define PLL_FWDDIVB		0x00007000
-#define CPC0_PLLMR1_FWDVB	0x00007000
-#define PLL_FWDDIVB_8		0x00000000
-#define PLL_FWDDIVB_7		0x00001000
-#define PLL_FWDDIVB_6		0x00002000
-#define PLL_FWDDIVB_5		0x00003000
-#define PLL_FWDDIVB_4		0x00004000
-#define PLL_FWDDIVB_3		0x00005000
-#define PLL_FWDDIVB_2		0x00006000
-#define PLL_FWDDIVB_1		0x00007000
-/* PLL tune bits */
-#define PLL_TUNE_MASK		0x000003FF
-#define PLL_TUNE_2_M_3		0x00000133	/*  2 <= M <= 3 */
-#define PLL_TUNE_4_M_6		0x00000134	/*  3 <  M <= 6 */
-#define PLL_TUNE_7_M_10		0x00000138	/*  6 <  M <= 10 */
-#define PLL_TUNE_11_M_14	0x0000013C	/* 10 <  M <= 14 */
-#define PLL_TUNE_15_M_40	0x0000023E	/* 14 <  M <= 40 */
-#define PLL_TUNE_VCO_LOW	0x00000000	/* 500MHz <= VCO <=  800MHz */
-#define PLL_TUNE_VCO_HI		0x00000080	/* 800MHz <  VCO <= 1000MHz */
-
-/* Defines for CPC0_PLLMR0 Register fields */
-/* CPU divisor */
-#define PLL_CPUDIV		0x00300000
-#define CPC0_PLLMR0_CCDV	0x00300000
-#define PLL_CPUDIV_1		0x00000000
-#define PLL_CPUDIV_2		0x00100000
-#define PLL_CPUDIV_3		0x00200000
-#define PLL_CPUDIV_4		0x00300000
-/* PLB divisor */
-#define PLL_PLBDIV		0x00030000
-#define CPC0_PLLMR0_CBDV	0x00030000
-#define PLL_PLBDIV_1		0x00000000
-#define PLL_PLBDIV_2		0x00010000
-#define PLL_PLBDIV_3		0x00020000
-#define PLL_PLBDIV_4		0x00030000
-/* OPB divisor */
-#define PLL_OPBDIV		0x00003000
-#define CPC0_PLLMR0_OPDV	0x00003000
-#define PLL_OPBDIV_1		0x00000000
-#define PLL_OPBDIV_2		0x00001000
-#define PLL_OPBDIV_3		0x00002000
-#define PLL_OPBDIV_4		0x00003000
-/* EBC divisor */
-#define PLL_EXTBUSDIV		0x00000300
-#define CPC0_PLLMR0_EPDV	0x00000300
-#define PLL_EXTBUSDIV_2		0x00000000
-#define PLL_EXTBUSDIV_3		0x00000100
-#define PLL_EXTBUSDIV_4		0x00000200
-#define PLL_EXTBUSDIV_5		0x00000300
-/* MAL divisor */
-#define PLL_MALDIV		0x00000030
-#define CPC0_PLLMR0_MPDV	0x00000030
-#define PLL_MALDIV_1		0x00000000
-#define PLL_MALDIV_2		0x00000010
-#define PLL_MALDIV_3		0x00000020
-#define PLL_MALDIV_4		0x00000030
-/* PCI divisor */
-#define PLL_PCIDIV		0x00000003
-#define CPC0_PLLMR0_PPFD	0x00000003
-#define PLL_PCIDIV_1		0x00000000
-#define PLL_PCIDIV_2		0x00000001
-#define PLL_PCIDIV_3		0x00000002
-#define PLL_PCIDIV_4		0x00000003
-
-/*
- * PLL settings for 266MHz CPU, 133MHz PLB/SDRAM, 66MHz EBC, 33MHz PCI,
- * assuming a 33.3MHz input clock to the 405EP.
- */
-#define PLLMR0_266_133_66	(PLL_CPUDIV_1 | PLL_PLBDIV_2 |     \
-				 PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 |  \
-				 PLL_MALDIV_1 | PLL_PCIDIV_4)
-#define PLLMR1_266_133_66	(PLL_FBKDIV_8  |			\
-				 PLL_FWDDIVA_3 | PLL_FWDDIVB_3 |	\
-				 PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
-
-#define PLLMR0_133_66_66_33	(PLL_CPUDIV_1 | PLL_PLBDIV_1 |		\
-				 PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 |	\
-				 PLL_MALDIV_1 | PLL_PCIDIV_4)
-#define PLLMR1_133_66_66_33	(PLL_FBKDIV_4  |			\
-				 PLL_FWDDIVA_6 | PLL_FWDDIVB_6 |	\
-				 PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
-#define PLLMR0_200_100_50_33	(PLL_CPUDIV_1 | PLL_PLBDIV_2 |		\
-				 PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 |	\
-				 PLL_MALDIV_1 | PLL_PCIDIV_4)
-#define PLLMR1_200_100_50_33	(PLL_FBKDIV_6  |			\
-				 PLL_FWDDIVA_4 | PLL_FWDDIVB_4 |	\
-				 PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
-#define PLLMR0_266_133_66_33	(PLL_CPUDIV_1 | PLL_PLBDIV_2 |		\
-				 PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 |	\
-				 PLL_MALDIV_1 | PLL_PCIDIV_4)
-#define PLLMR1_266_133_66_33	(PLL_FBKDIV_8  |			\
-				 PLL_FWDDIVA_3 | PLL_FWDDIVB_3 |	\
-				 PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
-#define PLLMR0_266_66_33_33	(PLL_CPUDIV_1 | PLL_PLBDIV_4 |		\
-				 PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 |	\
-				 PLL_MALDIV_1 | PLL_PCIDIV_2)
-#define PLLMR1_266_66_33_33	(PLL_FBKDIV_8  |			\
-				 PLL_FWDDIVA_3 | PLL_FWDDIVB_3 |	\
-				 PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
-#define PLLMR0_333_111_55_37	(PLL_CPUDIV_1 | PLL_PLBDIV_3 |		\
-				 PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 |	\
-				 PLL_MALDIV_1 | PLL_PCIDIV_3)
-#define PLLMR1_333_111_55_37	(PLL_FBKDIV_10  |			\
-				 PLL_FWDDIVA_3 | PLL_FWDDIVB_3 |	\
-				 PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI)
-#define PLLMR0_333_111_55_111	(PLL_CPUDIV_1 | PLL_PLBDIV_3 |		\
-				 PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 |	\
-				 PLL_MALDIV_1 | PLL_PCIDIV_1)
-#define PLLMR1_333_111_55_111	(PLL_FBKDIV_10  |			\
-				 PLL_FWDDIVA_3 | PLL_FWDDIVB_3 |	\
-				 PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI)
-
-#endif /* _PPC405EP_H_ */
diff --git a/arch/powerpc/include/asm/ppc405ex.h b/arch/powerpc/include/asm/ppc405ex.h
deleted file mode 100644
index 083405c..0000000
--- a/arch/powerpc/include/asm/ppc405ex.h
+++ /dev/null
@@ -1,82 +0,0 @@
-/*
- * (C) Copyright 2010
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef _PPC405EX_H_
-#define _PPC405EX_H_
-
-#define CONFIG_SDRAM_PPC4xx_IBM_DDR2	/* IBM DDR(2) controller */
-
-#define CONFIG_NAND_NDFC
-
-/* Memory mapped register */
-#define CONFIG_SYS_PERIPHERAL_BASE	0xef600000 /* Internal Peripherals */
-
-#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_PERIPHERAL_BASE + 0x0200)
-#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_PERIPHERAL_BASE + 0x0300)
-
-#define GPIO0_BASE		(CONFIG_SYS_PERIPHERAL_BASE + 0x0800)
-
-/* SDR */
-#define SDR0_SDCS0		0x0060
-#define SDR0_UART0		0x0120	/* UART0 Config */
-#define SDR0_UART1		0x0121	/* UART1 Config */
-#define SDR0_SRST		0x0200
-#define SDR0_CUST0		0x4000
-#define SDR0_PFC0		0x4100
-#define SDR0_PFC1		0x4101
-#define SDR0_MFR		0x4300	/* SDR0_MFR reg */
-
-#define SDR0_ECID0		0x0080
-#define SDR0_ECID1		0x0081
-#define SDR0_ECID2		0x0082
-#define SDR0_ECID3		0x0083
-
-#define SDR0_SDCS_SDD		(0x80000000 >> 31)
-
-#define SDR0_SRST_DMC		(0x80000000 >> 10)
-
-#define SDR0_CUST0_MUX_E_N_G_MASK	0xC0000000 /* Mux_Emac_NDFC_GPIO */
-#define SDR0_CUST0_MUX_EMAC_SEL		0x40000000 /* Emac Selection */
-#define SDR0_CUST0_MUX_NDFC_SEL		0x80000000 /* NDFC Selection */
-#define SDR0_CUST0_MUX_GPIO_SEL		0xC0000000 /* GPIO Selection */
-
-#define SDR0_CUST0_NDFC_EN_MASK		0x20000000 /* NDFC Enable Mask */
-#define SDR0_CUST0_NDFC_ENABLE		0x20000000 /* NDFC Enable */
-#define SDR0_CUST0_NDFC_DISABLE		0x00000000 /* NDFC Disable */
-
-#define SDR0_CUST0_NDFC_BW_MASK	  	0x10000000 /* NDFC Boot Width */
-#define SDR0_CUST0_NDFC_BW_16_BIT 	0x10000000 /* NDFC Boot Width= 16 Bit */
-#define SDR0_CUST0_NDFC_BW_8_BIT  	0x00000000 /* NDFC Boot Width=  8 Bit */
-
-#define SDR0_CUST0_NDFC_BP_MASK		0x0F000000 /* NDFC Boot Page */
-#define SDR0_CUST0_NDFC_BP_ENCODE(n)	((((u32)(n)) & 0xF) << 24)
-#define SDR0_CUST0_NDFC_BP_DECODE(n)	((((u32)(n)) >> 24) & 0xF)
-
-#define SDR0_CUST0_NDFC_BAC_MASK	0x00C00000 /* NDFC Boot Address Cycle */
-#define SDR0_CUST0_NDFC_BAC_ENCODE(n)	((((u32)(n)) & 0x3) << 22)
-#define SDR0_CUST0_NDFC_BAC_DECODE(n)	((((u32)(n)) >> 22) & 0x3)
-
-#define SDR0_CUST0_NDFC_ARE_MASK	0x00200000 /* NDFC Auto Read Enable */
-#define SDR0_CUST0_NDFC_ARE_ENABLE	0x00200000 /* NDFC Auto Read Enable */
-#define SDR0_CUST0_NDFC_ARE_DISABLE	0x00000000 /* NDFC Auto Read Disable */
-
-#define SDR0_CUST0_NRB_MASK		0x00100000 /* NDFC Ready / Busy */
-#define SDR0_CUST0_NRB_BUSY		0x00100000 /* Busy */
-#define SDR0_CUST0_NRB_READY		0x00000000 /* Ready */
-
-#define SDR0_PFC1_U1ME			0x02000000
-#define SDR0_PFC1_U0ME			0x00080000
-#define SDR0_PFC1_U0IM			0x00040000
-#define SDR0_PFC1_SIS			0x00020000
-#define SDR0_PFC1_DMAAEN		0x00010000
-#define SDR0_PFC1_DMADEN		0x00008000
-#define SDR0_PFC1_USBEN			0x00004000
-#define SDR0_PFC1_AHBSWAP		0x00000020
-#define SDR0_PFC1_USBBIGEN		0x00000010
-#define SDR0_PFC1_GPT_FREQ		0x0000000f
-
-#endif /* _PPC405EX_H_ */
diff --git a/arch/powerpc/include/asm/ppc405ez.h b/arch/powerpc/include/asm/ppc405ez.h
deleted file mode 100644
index 40cf8ed..0000000
--- a/arch/powerpc/include/asm/ppc405ez.h
+++ /dev/null
@@ -1,89 +0,0 @@
-/*
- * (C) Copyright 2010
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef _PPC405EZ_H_
-#define _PPC405EZ_H_
-
-#define CONFIG_NAND_NDFC
-
-/* Memory mapped register */
-#define CONFIG_SYS_PERIPHERAL_BASE	0xef600000 /* Internal Peripherals */
-
-#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_PERIPHERAL_BASE + 0x0300)
-#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_PERIPHERAL_BASE + 0x0400)
-
-#define GPIO0_BASE		(CONFIG_SYS_PERIPHERAL_BASE + 0x0700)
-#define GPIO1_BASE		(CONFIG_SYS_PERIPHERAL_BASE + 0x0800)
-
-/* DCR register */
-#define OCM0_PLBCR1	0x0020	/* OCM PLB3 Bank 1 Config */
-#define OCM0_PLBCR2	0x0021	/* OCM PLB3 Bank 2 Config */
-#define OCM0_PLBBEAR	0x0022	/* OCM PLB3 Bus Error Add */
-#define OCM0_DSRC1	0x0028	/* OCM D-side Bank 1 Config */
-#define OCM0_DSRC2	0x0029	/* OCM D-side Bank 2 Config */
-#define OCM0_ISRC1	0x002A	/* OCM I-side Bank 1Config */
-#define OCM0_ISRC2	0x002B	/* OCM I-side Bank 2 Config */
-#define OCM0_DISDPC	0x002C	/* OCM D-/I-side Data Par Chk */
-
-/* SDR register */
-#define SDR0_NAND0	0x4000
-#define SDR0_ULTRA0	0x4040
-#define SDR0_ULTRA1	0x4050
-#define SDR0_ICINTSTAT	0x4510
-
-/* CPR register */
-#define CPR0_PRIMAD	0x0080
-#define CPR0_PERD0	0x00e0
-#define CPR0_PERD1	0x00e1
-#define CPR0_PERC0	0x0180
-
-#define	MAL_DCR_BASE	0x380
-
-#define SDR_NAND0_NDEN		0x80000000
-#define SDR_NAND0_NDBTEN	0x40000000
-#define SDR_NAND0_NDBADR_MASK	0x30000000
-#define SDR_NAND0_NDBPG_MASK	0x0f000000
-#define SDR_NAND0_NDAREN	0x00800000
-#define SDR_NAND0_NDRBEN	0x00400000
-
-#define SDR_ULTRA0_NDGPIOBP	0x80000000
-#define SDR_ULTRA0_CSN_MASK	0x78000000
-#define SDR_ULTRA0_CSNSEL0	0x40000000
-#define SDR_ULTRA0_CSNSEL1	0x20000000
-#define SDR_ULTRA0_CSNSEL2	0x10000000
-#define SDR_ULTRA0_CSNSEL3	0x08000000
-#define SDR_ULTRA0_EBCRDYEN	0x04000000
-#define SDR_ULTRA0_SPISSINEN	0x02000000
-#define SDR_ULTRA0_NFSRSTEN	0x01000000
-
-#define SDR_ULTRA1_LEDNENABLE	0x40000000
-
-#define SDR_ICRX_STAT		0x80000000
-#define SDR_ICTX0_STAT		0x40000000
-#define SDR_ICTX1_STAT		0x20000000
-
-#define CPR_CLKUPD_ENPLLCH_EN	0x40000000 /* Enable CPR PLL Changes */
-#define CPR_CLKUPD_ENDVCH_EN	0x20000000 /* Enable CPR Sys. Div. Changes */
-#define CPR_PERD0_SPIDV_MASK	0x000F0000 /* SPI Clock Divider */
-
-#define PLLC_SRC_MASK		0x20000000 /* PLL feedback source */
-
-#define PLLD_FBDV_MASK		0x1F000000 /* PLL feedback divider value */
-#define PLLD_FWDVA_MASK		0x000F0000 /* PLL forward divider A value */
-#define PLLD_FWDVB_MASK		0x00000700 /* PLL forward divider B value */
-
-#define PRIMAD_CPUDV_MASK	0x0F000000 /* CPU Clock Divisor Mask */
-#define PRIMAD_PLBDV_MASK	0x000F0000 /* PLB Clock Divisor Mask */
-#define PRIMAD_OPBDV_MASK	0x00000F00 /* OPB Clock Divisor Mask */
-#define PRIMAD_EBCDV_MASK	0x0000000F /* EBC Clock Divisor Mask */
-
-#define PERD0_PWMDV_MASK	0xFF000000 /* PWM Divider Mask */
-#define PERD0_SPIDV_MASK	0x000F0000 /* SPI Divider Mask */
-#define PERD0_U0DV_MASK		0x0000FF00 /* UART 0 Divider Mask */
-#define PERD0_U1DV_MASK		0x000000FF /* UART 1 Divider Mask */
-
-#endif /* _PPC405EZ_H_ */
diff --git a/arch/powerpc/include/asm/ppc405gp.h b/arch/powerpc/include/asm/ppc405gp.h
deleted file mode 100644
index 0044a3a..0000000
--- a/arch/powerpc/include/asm/ppc405gp.h
+++ /dev/null
@@ -1,95 +0,0 @@
-/*
- * (C) Copyright 2010
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef _PPC405GP_H_
-#define _PPC405GP_H_
-
-#define CONFIG_SDRAM_PPC4xx_IBM_SDRAM	/* IBM SDRAM controller */
-
-/* Memory mapped register */
-#define CONFIG_SYS_PERIPHERAL_BASE	0xef600000 /* Internal Peripherals */
-
-#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_PERIPHERAL_BASE + 0x0300)
-#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_PERIPHERAL_BASE + 0x0400)
-
-#define GPIO0_BASE		(CONFIG_SYS_PERIPHERAL_BASE + 0x0700)
-
-/* DCR's */
-#define DCP0_CFGADDR	0x0014		/* Decompression controller addr reg */
-#define DCP0_CFGDATA	0x0015		/* Decompression controller data reg */
-#define OCM0_ISCNTL	0x0019	/* OCM I-side control reg */
-#define OCM0_DSARC	0x001a	/* OCM D-side address compare */
-#define OCM0_DSCNTL	0x001b	/* OCM D-side control */
-#define CPC0_PLLMR	0x00b0		/* PLL mode  register */
-#define CPC0_CR0	0x00b1		/* chip control register 0 */
-#define CPC0_CR1	0x00b2		/* chip control register 1 */
-#define CPC0_PSR	0x00b4		/* chip pin strapping reg */
-#define CPC0_EIRR	0x00b6		/* ext interrupt routing reg */
-#define CPC0_SR		0x00b8		/* Power management status */
-#define CPC0_ER		0x00b9		/* Power management enable */
-#define CPC0_FR		0x00ba		/* Power management force */
-#define CPC0_ECR	0x00aa		/* edge conditioner register */
-
-/* values for kiar register - indirect addressing of these regs */
-#define KCONF		0x40		/* decompression core config register */
-
-#define PLLMR_FWD_DIV_MASK	0xE0000000	/* Forward Divisor */
-#define PLLMR_FWD_DIV_BYPASS	0xE0000000
-#define PLLMR_FWD_DIV_3		0xA0000000
-#define PLLMR_FWD_DIV_4		0x80000000
-#define PLLMR_FWD_DIV_6		0x40000000
-
-#define PLLMR_FB_DIV_MASK	0x1E000000	/* Feedback Divisor */
-#define PLLMR_FB_DIV_1		0x02000000
-#define PLLMR_FB_DIV_2		0x04000000
-#define PLLMR_FB_DIV_3		0x06000000
-#define PLLMR_FB_DIV_4		0x08000000
-
-#define PLLMR_TUNING_MASK	0x01F80000
-
-#define PLLMR_CPU_TO_PLB_MASK	0x00060000	/* CPU:PLB Frequency Divisor */
-#define PLLMR_CPU_PLB_DIV_1	0x00000000
-#define PLLMR_CPU_PLB_DIV_2	0x00020000
-#define PLLMR_CPU_PLB_DIV_3	0x00040000
-#define PLLMR_CPU_PLB_DIV_4	0x00060000
-
-#define PLLMR_OPB_TO_PLB_MASK	0x00018000	/* OPB:PLB Frequency Divisor */
-#define PLLMR_OPB_PLB_DIV_1	0x00000000
-#define PLLMR_OPB_PLB_DIV_2	0x00008000
-#define PLLMR_OPB_PLB_DIV_3	0x00010000
-#define PLLMR_OPB_PLB_DIV_4	0x00018000
-
-#define PLLMR_PCI_TO_PLB_MASK	0x00006000	/* PCI:PLB Frequency Divisor */
-#define PLLMR_PCI_PLB_DIV_1	0x00000000
-#define PLLMR_PCI_PLB_DIV_2	0x00002000
-#define PLLMR_PCI_PLB_DIV_3	0x00004000
-#define PLLMR_PCI_PLB_DIV_4	0x00006000
-
-#define PLLMR_EXB_TO_PLB_MASK	0x00001800	/* External Bus:PLB Divisor */
-#define PLLMR_EXB_PLB_DIV_2	0x00000000
-#define PLLMR_EXB_PLB_DIV_3	0x00000800
-#define PLLMR_EXB_PLB_DIV_4	0x00001000
-#define PLLMR_EXB_PLB_DIV_5	0x00001800
-
-/* definitions for PPC405GPr (new mode strapping) */
-#define PLLMR_FWDB_DIV_MASK	0x00000007	/* Forward Divisor B */
-
-#define PSR_PLL_FWD_MASK	0xC0000000
-#define PSR_PLL_FDBACK_MASK	0x30000000
-#define PSR_PLL_TUNING_MASK	0x0E000000
-#define PSR_PLB_CPU_MASK	0x01800000
-#define PSR_OPB_PLB_MASK	0x00600000
-#define PSR_PCI_PLB_MASK	0x00180000
-#define PSR_EB_PLB_MASK		0x00060000
-#define PSR_ROM_WIDTH_MASK	0x00018000
-#define PSR_ROM_LOC		0x00004000
-#define PSR_PCI_ASYNC_EN	0x00001000
-#define PSR_PERCLK_SYNC_MODE_EN 0x00000800	/* PPC405GPr only */
-#define PSR_PCI_ARBIT_EN	0x00000400
-#define PSR_NEW_MODE_EN		0x00000020	/* PPC405GPr only */
-
-#endif /* _PPC405GP_H_ */
diff --git a/arch/powerpc/include/asm/ppc440.h b/arch/powerpc/include/asm/ppc440.h
deleted file mode 100644
index 0cfa88b..0000000
--- a/arch/powerpc/include/asm/ppc440.h
+++ /dev/null
@@ -1,154 +0,0 @@
-/*
- * (C) Copyright 2006
- * Sylvie Gohl,             AMCC/IBM, gohl.sylvie@fr.ibm.com
- * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
- * Thierry Roman,           AMCC/IBM, thierry_roman@fr.ibm.com
- * Alain Saurel,            AMCC/IBM, alain.saurel@fr.ibm.com
- * Robert Snyder,           AMCC/IBM, rob.snyder@fr.ibm.com
- *
- * (C) Copyright 2010
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0	IBM-pibs
- */
-
-#ifndef __PPC440_H__
-#define __PPC440_H__
-
-#define CONFIG_SYS_DCACHE_SIZE		(32 << 10)	/* For AMCC 440 CPUs */
-
-/*
- * DCRs & Related
- */
-
-/* Memory mapped registers */
-#define PCIL0_CFGADR	(CONFIG_SYS_PCI_BASE + 0x0ec00000)
-#define PCIL0_CFGDATA	(CONFIG_SYS_PCI_BASE + 0x0ec00004)
-#define PCIL0_CFGBASE	(CONFIG_SYS_PCI_BASE + 0x0ec80000)
-#define PCIL0_IOBASE	(CONFIG_SYS_PCI_BASE + 0x08000000)
-
-/* DCR registers */
-
-/* CPR register declarations */
-#define CPR0_PLLC	0x0040
-#define CPR0_PLLD	0x0060
-#define CPR0_PRIMAD0	0x0080
-#define CPR0_PRIMBD0	0x00a0
-#define CPR0_OPBD0	0x00c0
-#define CPR0_PERD	0x00e0
-#define CPR0_MALD	0x0100
-#define CPR0_SPCID	0x0120
-#define CPR0_ICFG	0x0140
-
-/* SDR register definations */
-#define SDR0_SDSTP0	0x0020
-#define SDR0_SDSTP1	0x0021
-#define SDR0_PINSTP	0x0040
-#define SDR0_SDCS0	0x0060
-#define SDR0_ECID0	0x0080
-#define SDR0_ECID1	0x0081
-#define SDR0_ECID2	0x0082
-#define SDR0_ECID3	0x0083
-#define SDR0_DDR0	0x00e1
-#define SDR0_EBC	0x0100
-#define SDR0_UART0	0x0120
-#define SDR0_UART1	0x0121
-#define SDR0_UART2	0x0122
-#define SDR0_UART3	0x0123
-#define SDR0_CP440	0x0180
-#define SDR0_XCR	0x01c0
-#define SDR0_XCR0	0x01c0
-#define SDR0_XPLLC	0x01c1
-#define SDR0_XPLLD	0x01c2
-#define SDR0_SRST	0x0200
-#define SDR0_SRST0	SDR0_SRST
-#define SDR0_SRST1	0x0201
-#define SDR0_AMP0	0x0240
-#define SDR0_AMP1	0x0241
-#define SDR0_USB0	0x0320
-#define SDR0_CUST0	0x4000
-#define SDR0_CUST1	0x4002
-#define SDR0_CUST2	0x4004
-#define SDR0_CUST3	0x4006
-#define SDR0_PFC0	0x4100
-#define SDR0_PFC1	0x4101
-#define SDR0_PFC2   	0x4102
-#define SDR0_PFC4	0x4104
-#define SDR0_MFR	0x4300
-
-#define SDR0_DDR0_DDRM_DECODE(n)	((((u32)(n)) >> 29) & 0x03)
-
-#define SDR0_PCI0_PAE_MASK		(0x80000000 >> 0)
-#define SDR0_XCR0_PAE_MASK		(0x80000000 >> 0)
-
-#define SDR0_PFC0_GEIE_MASK		0x00003e00
-#define SDR0_PFC0_GEIE_TRE		0x00003e00
-#define SDR0_PFC0_GEIE_NOTRE		0x00000000
-#define SDR0_PFC0_TRE_MASK		(0x80000000 >> 23)
-#define SDR0_PFC0_TRE_DISABLE		0x00000000
-#define SDR0_PFC0_TRE_ENABLE		(0x80000000 >> 23)
-
-/*
- * Core Configuration/MMU configuration for 440
- */
-#define CCR0_DAPUIB		0x00100000
-#define CCR0_DTB		0x00008000
-
-#define SDR0_SDCS_SDD		(0x80000000 >> 31)
-
-/* todo: move this code from macro offsets to struct */
-#define PCIL0_VENDID		(PCIL0_CFGBASE + PCI_VENDOR_ID )
-#define PCIL0_DEVID		(PCIL0_CFGBASE + PCI_DEVICE_ID )
-#define PCIL0_CMD		(PCIL0_CFGBASE + PCI_COMMAND )
-#define PCIL0_STATUS		(PCIL0_CFGBASE + PCI_STATUS )
-#define PCIL0_REVID		(PCIL0_CFGBASE + PCI_REVISION_ID )
-#define PCIL0_CLS		(PCIL0_CFGBASE + PCI_CLASS_CODE)
-#define PCIL0_CACHELS		(PCIL0_CFGBASE + PCI_CACHE_LINE_SIZE )
-#define PCIL0_LATTIM		(PCIL0_CFGBASE + PCI_LATENCY_TIMER )
-#define PCIL0_HDTYPE		(PCIL0_CFGBASE + PCI_HEADER_TYPE )
-#define PCIL0_BIST		(PCIL0_CFGBASE + PCI_BIST )
-#define PCIL0_BAR0		(PCIL0_CFGBASE + PCI_BASE_ADDRESS_0 )
-#define PCIL0_BAR1		(PCIL0_CFGBASE + PCI_BASE_ADDRESS_1 )
-#define PCIL0_BAR2		(PCIL0_CFGBASE + PCI_BASE_ADDRESS_2 )
-#define PCIL0_BAR3		(PCIL0_CFGBASE + PCI_BASE_ADDRESS_3 )
-#define PCIL0_BAR4		(PCIL0_CFGBASE + PCI_BASE_ADDRESS_4 )
-#define PCIL0_BAR5		(PCIL0_CFGBASE + PCI_BASE_ADDRESS_5 )
-#define PCIL0_CISPTR		(PCIL0_CFGBASE + PCI_CARDBUS_CIS )
-#define PCIL0_SBSYSVID		(PCIL0_CFGBASE + PCI_SUBSYSTEM_VENDOR_ID )
-#define PCIL0_SBSYSID		(PCIL0_CFGBASE + PCI_SUBSYSTEM_ID )
-#define PCIL0_EROMBA		(PCIL0_CFGBASE + PCI_ROM_ADDRESS )
-#define PCIL0_CAP		(PCIL0_CFGBASE + PCI_CAPABILITY_LIST )
-#define PCIL0_RES0		(PCIL0_CFGBASE + 0x0035 )
-#define PCIL0_RES1		(PCIL0_CFGBASE + 0x0036 )
-#define PCIL0_RES2		(PCIL0_CFGBASE + 0x0038 )
-#define PCIL0_INTLN		(PCIL0_CFGBASE + PCI_INTERRUPT_LINE )
-#define PCIL0_INTPN		(PCIL0_CFGBASE + PCI_INTERRUPT_PIN )
-
-#define PCIL0_MINGNT		(PCIL0_CFGBASE + PCI_MIN_GNT )
-#define PCIL0_MAXLTNCY		(PCIL0_CFGBASE + PCI_MAX_LAT )
-
-#define PCIL0_POM0LAL		(PCIL0_CFGBASE + 0x0068)
-#define PCIL0_POM0LAH		(PCIL0_CFGBASE + 0x006c)
-#define PCIL0_POM0SA		(PCIL0_CFGBASE + 0x0070)
-#define PCIL0_POM0PCIAL		(PCIL0_CFGBASE + 0x0074)
-#define PCIL0_POM0PCIAH		(PCIL0_CFGBASE + 0x0078)
-#define PCIL0_POM1LAL		(PCIL0_CFGBASE + 0x007c)
-#define PCIL0_POM1LAH		(PCIL0_CFGBASE + 0x0080)
-#define PCIL0_POM1SA		(PCIL0_CFGBASE + 0x0084)
-#define PCIL0_POM1PCIAL		(PCIL0_CFGBASE + 0x0088)
-#define PCIL0_POM1PCIAH		(PCIL0_CFGBASE + 0x008c)
-#define PCIL0_POM2SA		(PCIL0_CFGBASE + 0x0090)
-
-#define PCIL0_PIM0SA		(PCIL0_CFGBASE + 0x0098)
-#define PCIL0_PIM0LAL		(PCIL0_CFGBASE + 0x009c)
-#define PCIL0_PIM0LAH		(PCIL0_CFGBASE + 0x00a0)
-#define PCIL0_PIM1SA		(PCIL0_CFGBASE + 0x00a4)
-#define PCIL0_PIM1LAL		(PCIL0_CFGBASE + 0x00a8)
-#define PCIL0_PIM1LAH		(PCIL0_CFGBASE + 0x00ac)
-#define PCIL0_PIM2SA		(PCIL0_CFGBASE + 0x00b0)
-#define PCIL0_PIM2LAL		(PCIL0_CFGBASE + 0x00b4)
-#define PCIL0_PIM2LAH		(PCIL0_CFGBASE + 0x00b8)
-
-#define PCIL0_STS		(PCIL0_CFGBASE + 0x00e0)
-
-#endif	/* __PPC440_H__ */
diff --git a/arch/powerpc/include/asm/ppc440ep_gr.h b/arch/powerpc/include/asm/ppc440ep_gr.h
deleted file mode 100644
index c2c3abb..0000000
--- a/arch/powerpc/include/asm/ppc440ep_gr.h
+++ /dev/null
@@ -1,231 +0,0 @@
-/*
- * (C) Copyright 2010
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef _PPC440EP_GR_H_
-#define _PPC440EP_GR_H_
-
-#define CONFIG_SDRAM_PPC4xx_IBM_DDR	/* IBM DDR controller */
-
-#define CONFIG_NAND_NDFC
-
-/*
- * Some SoC specific registers (not common for all 440 SoC's)
- */
-
-/* Memory mapped registers */
-#define CONFIG_SYS_PERIPHERAL_BASE	0xef600000 /* Internal Peripherals */
-
-#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_PERIPHERAL_BASE + 0x0300)
-#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_PERIPHERAL_BASE + 0x0400)
-#define CONFIG_SYS_NS16550_COM3	(CONFIG_SYS_PERIPHERAL_BASE + 0x0500)
-#define CONFIG_SYS_NS16550_COM4	(CONFIG_SYS_PERIPHERAL_BASE + 0x0600)
-
-#define GPIO0_BASE		(CONFIG_SYS_PERIPHERAL_BASE + 0x0b00)
-#define GPIO1_BASE		(CONFIG_SYS_PERIPHERAL_BASE + 0x0c00)
-
-/* SDR's */
-#define SDR0_PCI0	0x0300
-#define SDR0_SDSTP2	0x4001
-#define SDR0_SDSTP3	0x4003
-
-#define SDR0_SDSTP1_PAE_MASK		(0x80000000 >> 21)
-#define SDR0_SDSTP1_PAME_MASK		(0x80000000 >> 27)
-
-/* Pin Function Control Register 1 */
-#define SDR0_PFC1_U1ME_MASK		0x02000000 /* UART1 Mode Enable */
-#define SDR0_PFC1_U1ME_DSR_DTR		0x00000000 /* UART1 in DSR/DTR Mode */
-#define SDR0_PFC1_U1ME_CTS_RTS		0x02000000 /* UART1 in CTS/RTS Mode */
-#define SDR0_PFC1_U0ME_MASK		0x00080000 /* UART0 Mode Enable */
-#define SDR0_PFC1_U0ME_DSR_DTR		0x00000000 /* UART0 in DSR/DTR Mode */
-#define SDR0_PFC1_U0ME_CTS_RTS		0x00080000 /* UART0 in CTS/RTS Mode */
-#define SDR0_PFC1_U0IM_MASK		0x00040000 /* UART0 Interface Mode */
-#define SDR0_PFC1_U0IM_8PINS		0x00000000 /* UART0 Interface Mode 8 pins */
-#define SDR0_PFC1_U0IM_4PINS		0x00040000 /* UART0 Interface Mode 4 pins */
-#define SDR0_PFC1_SIS_MASK		0x00020000 /* SCP or IIC1 Selection */
-#define SDR0_PFC1_SIS_SCP_SEL		0x00000000 /* SCP Selected */
-#define SDR0_PFC1_SIS_IIC1_SEL		0x00020000 /* IIC1 Selected */
-#define SDR0_PFC1_UES_MASK		0x00010000 /* USB2D_RX_Active / EBC_Hold
-						      Req Selection */
-#define SDR0_PFC1_UES_USB2D_SEL		0x00000000 /* USB2D_RX_Active Selected */
-#define SDR0_PFC1_UES_EBCHR_SEL		0x00010000 /* EBC_Hold Req Selected */
-#define SDR0_PFC1_DIS_MASK		0x00008000 /* DMA_Req(1) / UIC_IRQ(5)
-						      Selection */
-#define SDR0_PFC1_DIS_DMAR_SEL		0x00000000 /* DMA_Req(1) Selected */
-#define SDR0_PFC1_DIS_UICIRQ5_SEL	0x00008000 /* UIC_IRQ(5) Selected */
-#define SDR0_PFC1_ERE_MASK		0x00004000 /* EBC Mast.Ext.Req.En./GPIO0(27)
-						      Selection */
-#define SDR0_PFC1_ERE_EXTR_SEL		0x00000000 /* EBC Mast.Ext.Req.En.
-						      Selected */
-#define SDR0_PFC1_ERE_GPIO0_27_SEL	0x00004000 /* GPIO0(27) Selected */
-#define SDR0_PFC1_UPR_MASK		0x00002000 /* USB2 Device Packet Reject
-						      Selection */
-#define SDR0_PFC1_UPR_DISABLE		0x00000000 /* USB2 Device Packet Reject
-						      Disable */
-#define SDR0_PFC1_UPR_ENABLE		0x00002000 /* USB2 Device Packet Reject
-						      Enable */
-#define SDR0_PFC1_PLB_PME_MASK		0x00001000 /* PLB3/PLB4 Perf. Monitor Enable
-						      Selection */
-#define SDR0_PFC1_PLB_PME_PLB3_SEL	0x00000000 /* PLB3 Performance Monitor
-						      Enable */
-#define SDR0_PFC1_PLB_PME_PLB4_SEL	0x00001000 /* PLB3 Performance Monitor
-						      Enable */
-#define SDR0_PFC1_GFGGI_MASK		0x0000000F /* GPT Frequency Generation
-						      Gated In */
-
-/* USB Control Register */
-#define SDR0_USB0_USB_DEVSEL_MASK	0x00000002 /* USB Device Selection */
-#define SDR0_USB0_USB20D_DEVSEL		0x00000000 /* USB2.0 Device Selected */
-#define SDR0_USB0_USB11D_DEVSEL		0x00000002 /* USB1.1 Device Selected */
-#define SDR0_USB0_LEEN_MASK		0x00000001 /* Little Endian selection */
-#define SDR0_USB0_LEEN_DISABLE		0x00000000 /* Little Endian Disable */
-#define SDR0_USB0_LEEN_ENABLE		0x00000001 /* Little Endian Enable */
-
-/* Miscealleneaous Function Reg. */
-#define SDR0_MFR_ETH0_CLK_SEL_MASK	0x08000000 /* Ethernet0 Clock Select */
-#define SDR0_MFR_ETH0_CLK_SEL_EXT	0x00000000
-#define SDR0_MFR_ETH1_CLK_SEL_MASK	0x04000000 /* Ethernet1 Clock Select */
-#define SDR0_MFR_ETH1_CLK_SEL_EXT	0x00000000
-#define SDR0_MFR_ZMII_MODE_MASK		0x03000000 /* ZMII Mode Mask */
-#define SDR0_MFR_ZMII_MODE_MII		0x00000000 /* ZMII Mode MII */
-#define SDR0_MFR_ZMII_MODE_SMII		0x01000000 /* ZMII Mode SMII */
-#define SDR0_MFR_ZMII_MODE_RMII_10M	0x02000000 /* ZMII Mode RMII - 10 Mbs */
-#define SDR0_MFR_ZMII_MODE_RMII_100M	0x03000000 /* ZMII Mode RMII - 100 Mbs */
-#define SDR0_MFR_ZMII_MODE_BIT0		0x02000000 /* ZMII Mode Bit0 */
-#define SDR0_MFR_ZMII_MODE_BIT1		0x01000000 /* ZMII Mode Bit1 */
-#define SDR0_MFR_ZM_ENCODE(n)		((((u32)(n)) & 0x3) << 24)
-#define SDR0_MFR_ZM_DECODE(n)		((((u32)(n)) << 24) & 0x3)
-
-#define SDR0_MFR_ERRATA3_EN0		0x00800000
-#define SDR0_MFR_ERRATA3_EN1		0x00400000
-#define SDR0_MFR_PKT_REJ_MASK		0x00180000 /* Pkt Rej. Enable Mask */
-#define SDR0_MFR_PKT_REJ_EN		0x00180000 /* Pkt Rej. Ena. on both EMAC3 0-1 */
-#define SDR0_MFR_PKT_REJ_EN0		0x00100000 /* Pkt Rej. Enable on EMAC3(0) */
-#define SDR0_MFR_PKT_REJ_EN1		0x00080000 /* Pkt Rej. Enable on EMAC3(1) */
-#define SDR0_MFR_PKT_REJ_POL		0x00200000 /* Packet Reject Polarity */
-
-/* CUST0 Customer Configuration Register0 */
-#define SDR0_CUST0_MUX_E_N_G_MASK	0xC0000000 /* Mux_Emac_NDFC_GPIO */
-#define SDR0_CUST0_MUX_EMAC_SEL		0x40000000 /* Emac Selection */
-#define SDR0_CUST0_MUX_NDFC_SEL		0x80000000 /* NDFC Selection */
-#define SDR0_CUST0_MUX_GPIO_SEL		0xC0000000 /* GPIO Selection */
-
-#define SDR0_CUST0_NDFC_EN_MASK		0x20000000 /* NDFC Enable Mask */
-#define SDR0_CUST0_NDFC_ENABLE		0x20000000 /* NDFC Enable */
-#define SDR0_CUST0_NDFC_DISABLE		0x00000000 /* NDFC Disable */
-
-#define SDR0_CUST0_NDFC_BW_MASK		0x10000000 /* NDFC Boot Width */
-#define SDR0_CUST0_NDFC_BW_16_BIT	0x10000000 /* NDFC Boot Width = 16 Bit */
-#define SDR0_CUST0_NDFC_BW_8_BIT	0x00000000 /* NDFC Boot Width =  8 Bit */
-
-#define SDR0_CUST0_NDFC_BP_MASK		0x0F000000 /* NDFC Boot Page */
-#define SDR0_CUST0_NDFC_BP_ENCODE(n)	((((u32)(n)) & 0xF) << 24)
-#define SDR0_CUST0_NDFC_BP_DECODE(n)	((((u32)(n)) >> 24) & 0xF)
-
-#define SDR0_CUST0_NDFC_BAC_MASK	0x00C00000 /* NDFC Boot Address Cycle */
-#define SDR0_CUST0_NDFC_BAC_ENCODE(n)	((((u32)(n)) & 0x3) << 22)
-#define SDR0_CUST0_NDFC_BAC_DECODE(n)	((((u32)(n)) >> 22) & 0x3)
-
-#define SDR0_CUST0_NDFC_ARE_MASK	0x00200000 /* NDFC Auto Read Enable */
-#define SDR0_CUST0_NDFC_ARE_ENABLE	0x00200000 /* NDFC Auto Read Enable */
-#define SDR0_CUST0_NDFC_ARE_DISABLE	0x00000000 /* NDFC Auto Read Disable */
-
-#define SDR0_CUST0_NRB_MASK		0x00100000 /* NDFC Ready / Busy */
-#define SDR0_CUST0_NRB_BUSY		0x00100000 /* Busy */
-#define SDR0_CUST0_NRB_READY		0x00000000 /* Ready */
-
-#define SDR0_CUST0_NDRSC_MASK		0x0000FFF0 /* NDFC Device Reset Count Mask */
-#define SDR0_CUST0_NDRSC_ENCODE(n)	((((u32)(n)) & 0xFFF) << 4)
-#define SDR0_CUST0_NDRSC_DECODE(n)	((((u32)(n)) >> 4) & 0xFFF)
-
-#define SDR0_CUST0_CHIPSELGAT_MASK	0x0000000F /* Chip Select Gating Mask */
-#define SDR0_CUST0_CHIPSELGAT_DIS	0x00000000 /* Chip Select Gating Disable */
-#define SDR0_CUST0_CHIPSELGAT_ENALL	0x0000000F /*All Chip Select Gating Enable*/
-#define SDR0_CUST0_CHIPSELGAT_EN0	0x00000008 /* Chip Select0 Gating Enable */
-#define SDR0_CUST0_CHIPSELGAT_EN1	0x00000004 /* Chip Select1 Gating Enable */
-#define SDR0_CUST0_CHIPSELGAT_EN2	0x00000002 /* Chip Select2 Gating Enable */
-#define SDR0_CUST0_CHIPSELGAT_EN3	0x00000001 /* Chip Select3 Gating Enable */
-
-#define SDR0_SRST_DMC			0x00200000
-
-#define PLLSYS0_ENG_MASK	0x80000000	/* 0 = SysClk, 1 = PLL VCO */
-#define PLLSYS0_SRC_MASK	0x40000000	/* 0 = PLL A, 1 = PLL B */
-#define PLLSYS0_SEL_MASK	0x38000000	/* 0 = PLL, 1 = CPU, 5 = PerClk */
-#define PLLSYS0_TUNE_MASK	0x07fe0000	/* PLL Tune bits */
-#define PLLSYS0_FB_DIV_MASK	0x0001f000	/* Feedback divisor */
-#define PLLSYS0_FWD_DIV_A_MASK	0x00000f00	/* Fwd Div A */
-#define PLLSYS0_FWD_DIV_B_MASK	0x000000e0	/* Fwd Div B */
-#define PLLSYS0_PRI_DIV_B_MASK	0x0000001c	/* PLL Primary Divisor B */
-#define PLLSYS0_OPB_DIV_MASK	0x00000003	/* OPB Divisor */
-
-#define PLLC_ENG_MASK		0x20000000  /* PLL primary forward divisor source */
-#define PLLC_SRC_MASK		0x20000000  /* PLL feedback source   */
-#define PLLD_FBDV_MASK		0x1f000000  /* PLL Feedback Divisor  */
-#define PLLD_FWDVA_MASK		0x000f0000  /* PLL Forward Divisor A */
-#define PLLD_FWDVB_MASK		0x00000700  /* PLL Forward Divisor B */
-#define PLLD_LFBDV_MASK		0x0000003f  /* PLL Local Feedback Divisor */
-
-#define OPBDDV_MASK		0x03000000  /* OPB Clock Divisor Register */
-#define PERDV_MASK		0x07000000  /* Peripheral Clock Divisor */
-#define PRADV_MASK		0x07000000  /* Primary Divisor A */
-#define PRBDV_MASK		0x07000000  /* Primary Divisor B */
-#define SPCID_MASK		0x03000000  /* Sync PCI Divisor  */
-
-/* Strap 1 Register */
-#define PLLSYS1_LF_DIV_MASK	0xfc000000	/* PLL Local Feedback Divisor */
-#define PLLSYS1_PERCLK_DIV_MASK 0x03000000	/* Peripheral Clk Divisor */
-#define PLLSYS1_MAL_DIV_MASK	0x00c00000	/* MAL Clk Divisor */
-#define PLLSYS1_RW_MASK		0x00300000	/* ROM width */
-#define PLLSYS1_EAR_MASK	0x00080000	/* ERAP Address reset vector */
-#define PLLSYS1_PAE_MASK	0x00040000	/* PCI arbitor enable */
-#define PLLSYS1_PCHE_MASK	0x00020000	/* PCI host config enable */
-#define PLLSYS1_PISE_MASK	0x00010000	/* PCI init seq. enable */
-#define PLLSYS1_PCWE_MASK	0x00008000	/* PCI local cpu wait enable */
-#define PLLSYS1_PPIM_MASK	0x00007800	/* PCI inbound map */
-#define PLLSYS1_PR64E_MASK	0x00000400	/* PCI init Req64 enable */
-#define PLLSYS1_PXFS_MASK	0x00000300	/* PCI-X Freq Sel */
-#define PLLSYS1_RSVD_MASK	0x00000080	/* RSVD */
-#define PLLSYS1_PDM_MASK	0x00000040	/* PCI-X Driver Mode */
-#define PLLSYS1_EPS_MASK	0x00000038	/* Ethernet Pin Select */
-#define PLLSYS1_RMII_MASK	0x00000004	/* RMII Mode */
-#define PLLSYS1_TRE_MASK	0x00000002	/* GPIO Trace Enable */
-#define PLLSYS1_NTO1_MASK	0x00000001	/* CPU:PLB N-to-1 ratio */
-
-#define CPR0_ICFG_RLI_MASK	0x80000000
-#define CPR0_ICFG_ICS_MASK	0x00000007
-#define CPR0_SPCID_SPCIDV0_MASK	0x03000000
-#define CPR0_SPCID_SPCIDV0_DIV1	0x01000000
-#define CPR0_SPCID_SPCIDV0_DIV2	0x02000000
-#define CPR0_SPCID_SPCIDV0_DIV3	0x03000000
-#define CPR0_SPCID_SPCIDV0_DIV4	0x00000000
-#define CPR0_PERD_PERDV0_MASK	0x07000000
-
-#define PCI_MMIO_LCR_BASE	(CONFIG_SYS_PCI_BASE + 0x0f400000) /* Real =>
-								      0x0EF400000 */
-
-/* PCI Master Local Configuration Registers */
-#define PCIL0_PMM0LA		(PCI_MMIO_LCR_BASE + 0x00) /* PMM0 Local Address */
-#define PCIL0_PMM0MA		(PCI_MMIO_LCR_BASE + 0x04) /* PMM0 Mask/Attribute */
-#define PCIL0_PMM0PCILA		(PCI_MMIO_LCR_BASE + 0x08) /* PMM0 PCI Low Address */
-#define PCIL0_PMM0PCIHA		(PCI_MMIO_LCR_BASE + 0x0C) /* PMM0 PCI High Address */
-#define PCIL0_PMM1LA		(PCI_MMIO_LCR_BASE + 0x10) /* PMM1 Local Address */
-#define PCIL0_PMM1MA		(PCI_MMIO_LCR_BASE + 0x14) /* PMM1 Mask/Attribute */
-#define PCIL0_PMM1PCILA		(PCI_MMIO_LCR_BASE + 0x18) /* PMM1 PCI Low Address */
-#define PCIL0_PMM1PCIHA		(PCI_MMIO_LCR_BASE + 0x1C) /* PMM1 PCI High Address */
-#define PCIL0_PMM2LA		(PCI_MMIO_LCR_BASE + 0x20) /* PMM2 Local Address */
-#define PCIL0_PMM2MA		(PCI_MMIO_LCR_BASE + 0x24) /* PMM2 Mask/Attribute */
-#define PCIL0_PMM2PCILA		(PCI_MMIO_LCR_BASE + 0x28) /* PMM2 PCI Low Address */
-#define PCIL0_PMM2PCIHA		(PCI_MMIO_LCR_BASE + 0x2C) /* PMM2 PCI High Address */
-
-/* PCI Target Local Configuration Registers */
-#define PCIL0_PTM1MS		(PCI_MMIO_LCR_BASE + 0x30) /* PTM1 Memory Size/
-							      Attribute */
-#define PCIL0_PTM1LA		(PCI_MMIO_LCR_BASE + 0x34) /* PTM1 Local Addr. Reg */
-#define PCIL0_PTM2MS		(PCI_MMIO_LCR_BASE + 0x38) /* PTM2 Memory Size/
-							      Attribute */
-#define PCIL0_PTM2LA		(PCI_MMIO_LCR_BASE + 0x3C) /* PTM2 Local Addr. Reg */
-
-#endif /* _PPC440EP_GR_H_ */
diff --git a/arch/powerpc/include/asm/ppc440epx_grx.h b/arch/powerpc/include/asm/ppc440epx_grx.h
deleted file mode 100644
index 93c3e2e..0000000
--- a/arch/powerpc/include/asm/ppc440epx_grx.h
+++ /dev/null
@@ -1,453 +0,0 @@
-/*
- * (C) Copyright 2010
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef _PPC440EPX_GRX_H_
-#define _PPC440EPX_GRX_H_
-
-#define CONFIG_SDRAM_PPC4xx_DENALI_DDR2	/* Denali DDR(2) controller */
-
-#define CONFIG_NAND_NDFC
-
-/*
- * Some SoC specific registers (not common for all 440 SoC's)
- */
-
-/* Memory mapped registers */
-#define CONFIG_SYS_PERIPHERAL_BASE	0xef600000 /* Internal Peripherals */
-
-#define SPI0_MODE		(CONFIG_SYS_PERIPHERAL_BASE + 0x0090)
-
-#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_PERIPHERAL_BASE + 0x0300)
-#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_PERIPHERAL_BASE + 0x0400)
-#define CONFIG_SYS_NS16550_COM3	(CONFIG_SYS_PERIPHERAL_BASE + 0x0500)
-#define CONFIG_SYS_NS16550_COM4	(CONFIG_SYS_PERIPHERAL_BASE + 0x0600)
-
-#define GPIO0_BASE		(CONFIG_SYS_PERIPHERAL_BASE + 0x0b00)
-#define GPIO1_BASE		(CONFIG_SYS_PERIPHERAL_BASE + 0x0c00)
-
-/* DCR */
-#define CPM0_ER			0x00b0
-#define CPM1_ER			0x00f0
-#define PLB3A0_ACR		0x0077
-#define PLB4A0_ACR		0x0081
-#define PLB4A1_ACR		0x0089
-#define OPB2PLB40_BCTRL		0x0350
-#define P4P3BO0_CFG		0x0026
-
-/* SDR */
-#define SDR0_DDRCFG		0x00e0
-#define SDR0_PCI0		0x0300
-#define SDR0_SDSTP2		0x4001
-#define SDR0_SDSTP3		0x4003
-#define SDR0_EMAC0RXST 		0x4301
-#define SDR0_EMAC0TXST		0x4302
-#define SDR0_CRYP0		0x4500
-
-#define SDR0_SDSTP1_PAE_MASK		(0x80000000 >> 21)
-#define SDR0_SDSTP1_PAME_MASK		(0x80000000 >> 27)
-
-/* Pin Function Control Register 1 */
-#define SDR0_PFC1_U1ME_MASK		0x02000000 /* UART1 Mode Enable */
-#define SDR0_PFC1_U1ME_DSR_DTR		0x00000000 /* UART1 in DSR/DTR Mode */
-#define SDR0_PFC1_U1ME_CTS_RTS		0x02000000 /* UART1 in CTS/RTS Mode */
-#define SDR0_PFC1_SELECT_MASK		0x01C00000 /* Ethernet Pin Select
-						      EMAC 0 */
-#define SDR0_PFC1_SELECT_CONFIG_1_1	0x00C00000 /* 1xMII   using RGMII
-						      bridge */
-#define SDR0_PFC1_SELECT_CONFIG_1_2	0x00000000 /* 1xMII   using  ZMII
-						      bridge */
-#define SDR0_PFC1_SELECT_CONFIG_2	0x00C00000 /* 1xGMII  using RGMII
-						      bridge */
-#define SDR0_PFC1_SELECT_CONFIG_3	0x01000000 /* 1xTBI   using RGMII
-						      bridge */
-#define SDR0_PFC1_SELECT_CONFIG_4	0x01400000 /* 2xRGMII using RGMII
-						      bridge */
-#define SDR0_PFC1_SELECT_CONFIG_5	0x01800000 /* 2xRTBI  using RGMII
-						      bridge */
-#define SDR0_PFC1_SELECT_CONFIG_6	0x00800000 /* 2xSMII  using  ZMII
-						      bridge */
-#define SDR0_PFC1_U0ME_MASK		0x00080000 /* UART0 Mode Enable */
-#define SDR0_PFC1_U0ME_DSR_DTR		0x00000000 /* UART0 in DSR/DTR Mode */
-#define SDR0_PFC1_U0ME_CTS_RTS		0x00080000 /* UART0 in CTS/RTS Mode */
-#define SDR0_PFC1_U0IM_MASK		0x00040000 /* UART0 Interface Mode */
-#define SDR0_PFC1_U0IM_8PINS		0x00000000 /* UART0 Interface Mode 8 pins */
-#define SDR0_PFC1_U0IM_4PINS		0x00040000 /* UART0 Interface Mode 4 pins */
-#define SDR0_PFC1_SIS_MASK		0x00020000 /* SCP or IIC1 Selection */
-#define SDR0_PFC1_SIS_SCP_SEL		0x00000000 /* SCP Selected */
-#define SDR0_PFC1_SIS_IIC1_SEL		0x00020000 /* IIC1 Selected */
-#define SDR0_PFC1_UES_MASK		0x00010000 /* USB2D_RX_Active / EBC_Hold
-						      Req Selection */
-#define SDR0_PFC1_UES_USB2D_SEL		0x00000000 /* USB2D_RX_Active Selected */
-#define SDR0_PFC1_UES_EBCHR_SEL		0x00010000 /* EBC_Hold Req Selected */
-#define SDR0_PFC1_DIS_MASK		0x00008000 /* DMA_Req(1) / UIC_IRQ(5)
-						      Selection */
-#define SDR0_PFC1_DIS_DMAR_SEL		0x00000000 /* DMA_Req(1) Selected */
-#define SDR0_PFC1_DIS_UICIRQ5_SEL	0x00008000 /* UIC_IRQ(5) Selected */
-#define SDR0_PFC1_ERE_MASK		0x00004000 /* EBC Mast.Ext.Req.En./GPIO0(27)
-						      Selection */
-#define SDR0_PFC1_ERE_EXTR_SEL		0x00000000 /* EBC Mast.Ext.Req.En.
-						      Selected */
-#define SDR0_PFC1_ERE_GPIO0_27_SEL	0x00004000 /* GPIO0(27) Selected */
-#define SDR0_PFC1_UPR_MASK		0x00002000 /* USB2 Device Packet Reject
-						      Selection */
-#define SDR0_PFC1_UPR_DISABLE		0x00000000 /* USB2 Device Packet Reject
-						      Disable */
-#define SDR0_PFC1_UPR_ENABLE		0x00002000 /* USB2 Device Packet Reject
-						      Enable */
-#define SDR0_PFC1_PLB_PME_MASK		0x00001000 /* PLB3/PLB4 Perf. Monitor Enable
-						      Selection */
-#define SDR0_PFC1_PLB_PME_PLB3_SEL	0x00000000 /* PLB3 Performance Monitor
-						      Enable */
-#define SDR0_PFC1_PLB_PME_PLB4_SEL	0x00001000 /* PLB3 Performance Monitor
-						      Enable */
-#define SDR0_PFC1_GFGGI_MASK		0x0000000F /* GPT Frequency Generation
-						      Gated In */
-
-#define SDR0_PFC2_SELECT_MASK		0xe0000000 /* Ethernet Pin select EMAC1 */
-#define SDR0_PFC2_SELECT_CONFIG_1_1	0x60000000 /* 1xMII   using RGMII bridge */
-#define SDR0_PFC2_SELECT_CONFIG_1_2	0x00000000 /* 1xMII   using  ZMII bridge */
-#define SDR0_PFC2_SELECT_CONFIG_2	0x60000000 /* 1xGMII  using RGMII bridge */
-#define SDR0_PFC2_SELECT_CONFIG_3	0x80000000 /* 1xTBI   using RGMII bridge */
-#define SDR0_PFC2_SELECT_CONFIG_4	0xa0000000 /* 2xRGMII using RGMII bridge */
-#define SDR0_PFC2_SELECT_CONFIG_5	0xc0000000 /* 2xRTBI  using RGMII bridge */
-#define SDR0_PFC2_SELECT_CONFIG_6	0x40000000 /* 2xSMII  using  ZMII bridge */
-
-#define SDR0_USB2D0CR	0x0320
-#define SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK 0x00000004 /* USB 2.0 Device/EBC
-							 Master Selection */
-#define SDR0_USB2D0CR_USB2DEV_SELECTION	0x00000004 /* USB 2.0 Device Selection*/
-#define SDR0_USB2D0CR_EBC_SELECTION	0x00000000 /* EBC Selection */
-
-#define SDR0_USB2D0CR_USB_DEV_INT_SEL_MASK 0x00000002 /* USB Device Interface
-							 Selection */
-#define SDR0_USB2D0CR_USB20D_DEVSEL	0x00000000 /* USB2.0 Device Selected */
-#define SDR0_USB2D0CR_USB11D_DEVSEL	0x00000002 /* USB1.1 Device Selected */
-
-#define SDR0_USB2D0CR_LEEN_MASK		0x00000001 /* Little Endian selection */
-#define SDR0_USB2D0CR_LEEN_DISABLE	0x00000000 /* Little Endian Disable */
-#define SDR0_USB2D0CR_LEEN_ENABLE	0x00000001 /* Little Endian Enable */
-
-/* USB2 Host Control Register */
-#define SDR0_USB2H0CR		0x0340
-#define SDR0_USB2H0CR_WDINT_MASK	0x00000001 /* Host UTMI Word Interface*/
-#define SDR0_USB2H0CR_WDINT_8BIT_60MHZ	0x00000000 /* 8-bit/60MHz */
-#define SDR0_USB2H0CR_WDINT_16BIT_30MHZ	0x00000001 /* 16-bit/30MHz */
-#define SDR0_USB2H0CR_EFLADJ_MASK	0x0000007e /* EHCI Frame Length
-						      Adjustment */
-/* USB2PHY0 Control Register */
-#define SDR0_USB2PHY0CR		0x4103
-#define SDR0_USB2PHY0CR_UTMICN_MASK	0x00100000
-
-	/*  PHY UTMI interface connection */
-#define SDR0_USB2PHY0CR_UTMICN_DEV	0x00000000 /* Device support */
-#define SDR0_USB2PHY0CR_UTMICN_HOST	0x00100000 /* Host support */
-
-#define SDR0_USB2PHY0CR_DWNSTR_MASK	0x00400000 /* Select downstream port mode */
-#define SDR0_USB2PHY0CR_DWNSTR_DEV	0x00000000 /* Device */
-#define SDR0_USB2PHY0CR_DWNSTR_HOST	0x00400000 /* Host   */
-
-/* VBus detect (Device mode only)  */
-#define SDR0_USB2PHY0CR_DVBUS_MASK	0x00800000
-/* Pull-up resistance on D+ is disabled */
-#define SDR0_USB2PHY0CR_DVBUS_PURDIS	0x00000000
-/* Pull-up resistance on D+ is enabled */
-#define SDR0_USB2PHY0CR_DVBUS_PUREN	0x00800000
-
-/* PHY UTMI data width and clock select  */
-#define SDR0_USB2PHY0CR_WDINT_MASK	0x01000000
-#define SDR0_USB2PHY0CR_WDINT_8BIT_60MHZ 0x00000000 /* 8-bit data/60MHz */
-#define SDR0_USB2PHY0CR_WDINT_16BIT_30MHZ 0x01000000 /* 16-bit data/30MHz */
-
-#define SDR0_USB2PHY0CR_LOOPEN_MASK	0x02000000 /* Loop back test enable  */
-#define SDR0_USB2PHY0CR_LOOP_ENABLE	0x00000000 /* Loop back disabled */
-/* Loop back enabled (only test purposes) */
-#define SDR0_USB2PHY0CR_LOOP_DISABLE	0x02000000
-
-/* Force XO block on during a suspend  */
-#define SDR0_USB2PHY0CR_XOON_MASK	0x04000000
-#define SDR0_USB2PHY0CR_XO_ON		0x00000000 /* PHY XO block is powered-on */
-/* PHY XO block is powered-off when all ports are suspended */
-#define SDR0_USB2PHY0CR_XO_OFF		0x04000000
-
-#define SDR0_USB2PHY0CR_PWRSAV_MASK	0x08000000 /* Select PHY power-save mode  */
-#define SDR0_USB2PHY0CR_PWRSAV_OFF	0x00000000 /* Non-power-save mode */
-#define SDR0_USB2PHY0CR_PWRSAV_ON	0x08000000 /* Power-save mode. Valid only
-						      for full-speed operation */
-
-#define SDR0_USB2PHY0CR_XOREF_MASK	0x10000000 /* Select reference clock
-						      source  */
-#define SDR0_USB2PHY0CR_XOREF_INTERNAL	0x00000000 /* PHY PLL uses chip internal
-						      48M clock as a reference */
-#define SDR0_USB2PHY0CR_XOREF_XO	0x10000000 /* PHY PLL uses internal XO
-						      block output as a reference */
-
-#define SDR0_USB2PHY0CR_XOCLK_MASK	0x20000000 /* Select clock for XO
-						      block*/
-#define SDR0_USB2PHY0CR_XOCLK_EXTERNAL	0x00000000 /* PHY macro used an external
-						      clock */
-#define SDR0_USB2PHY0CR_XOCLK_CRYSTAL	0x20000000 /* PHY macro uses the clock
-						      from a crystal */
-
-#define SDR0_USB2PHY0CR_CLKSEL_MASK	0xc0000000 /* Select ref clk freq */
-#define SDR0_USB2PHY0CR_CLKSEL_12MHZ	0x00000000 /* Select ref clk freq
-						      = 12 MHz */
-#define SDR0_USB2PHY0CR_CLKSEL_48MHZ	0x40000000 /* Select ref clk freq
-						      = 48 MHz */
-#define SDR0_USB2PHY0CR_CLKSEL_24MHZ	0x80000000 /* Select ref clk freq
-						      = 24 MHz */
-
-/* USB2.0 Device */
-/*
- * todo: check if this can be completely removed, only used in
- * cpu/ppc4xx/usbdev.c. And offsets are completely wrong. This could
- * never have actually worked. Best probably is to remove this
- * usbdev.c file completely (and these defines).
- */
-#define USB2D0_BASE         CONFIG_SYS_USB2D0_BASE
-
-#define USB2D0_INTRIN       (USB2D0_BASE + 0x00000000)
-
-#define USB2D0_INTRIN       (USB2D0_BASE + 0x00000000) /* Interrupt register for
-				Endpoint 0 plus IN Endpoints 1 to 3 */
-#define USB2D0_POWER        (USB2D0_BASE + 0x00000000) /* Power management
-				register */
-#define USB2D0_FADDR        (USB2D0_BASE + 0x00000000) /* Function address
-				register */
-#define USB2D0_INTRINE      (USB2D0_BASE + 0x00000000) /* Interrupt enable
-				register for USB2D0_INTRIN */
-#define USB2D0_INTROUT      (USB2D0_BASE + 0x00000000) /* Interrupt register for
-				OUT Endpoints 1 to 3 */
-#define USB2D0_INTRUSBE     (USB2D0_BASE + 0x00000000) /* Interrupt enable
-				register for USB2D0_INTRUSB */
-#define USB2D0_INTRUSB      (USB2D0_BASE + 0x00000000) /* Interrupt register for
-				common USB interrupts */
-#define USB2D0_INTROUTE     (USB2D0_BASE + 0x00000000) /* Interrupt enable
-				register for IntrOut */
-#define USB2D0_TSTMODE      (USB2D0_BASE + 0x00000000) /* Enables the USB 2.0
-				test modes */
-#define USB2D0_INDEX        (USB2D0_BASE + 0x00000000) /* Index register for
-			     selecting the Endpoint status/control registers */
-#define USB2D0_FRAME        (USB2D0_BASE + 0x00000000) /* Frame number */
-#define USB2D0_INCSR0       (USB2D0_BASE + 0x00000000) /* Control Status
-	  register for Endpoint 0. (Index register set to select Endpoint 0) */
-#define USB2D0_INCSR        (USB2D0_BASE + 0x00000000) /* Control Status
-       register for IN Endpoint. (Index register set to select Endpoints 13) */
-#define USB2D0_INMAXP       (USB2D0_BASE + 0x00000000) /* Maximum packet
-	   size for IN Endpoint. (Index register set to select Endpoints 13) */
-#define USB2D0_OUTCSR       (USB2D0_BASE + 0x00000000) /* Control Status
-      register for OUT Endpoint. (Index register set to select Endpoints 13) */
-#define USB2D0_OUTMAXP      (USB2D0_BASE + 0x00000000) /* Maximum packet
-	  size for OUT Endpoint. (Index register set to select Endpoints 13) */
-#define USB2D0_OUTCOUNT0    (USB2D0_BASE + 0x00000000) /* Number of received
-	 bytes in Endpoint 0 FIFO. (Index register set to select Endpoint 0) */
-#define USB2D0_OUTCOUNT     (USB2D0_BASE + 0x00000000) /* Number of bytes in
-	      OUT Endpoint FIFO. (Index register set to select Endpoints 13) */
-
-/* Miscealleneaous Function Reg. */
-#define SDR0_MFR_ETH0_CLK_SEL_MASK	0x08000000 /* Ethernet0 Clock Select */
-#define SDR0_MFR_ETH0_CLK_SEL_EXT	0x00000000
-#define SDR0_MFR_ETH1_CLK_SEL_MASK	0x04000000 /* Ethernet1 Clock Select */
-#define SDR0_MFR_ETH1_CLK_SEL_EXT	0x00000000
-#define SDR0_MFR_ZMII_MODE_MASK		0x03000000 /* ZMII Mode Mask */
-#define SDR0_MFR_ZMII_MODE_MII		0x00000000 /* ZMII Mode MII */
-#define SDR0_MFR_ZMII_MODE_SMII		0x01000000 /* ZMII Mode SMII */
-#define SDR0_MFR_ZMII_MODE_BIT0		0x02000000 /* ZMII Mode Bit0 */
-#define SDR0_MFR_ZMII_MODE_BIT1		0x01000000 /* ZMII Mode Bit1 */
-#define SDR0_MFR_ZM_ENCODE(n)		((((u32)(n)) & 0x3) << 24)
-#define SDR0_MFR_ZM_DECODE(n)		((((u32)(n)) << 24) & 0x3)
-#define SDR0_MFR_PKT_REJ_MASK		0x00300000 /* Pkt Rej. Enable Mask */
-#define SDR0_MFR_PKT_REJ_EN		0x00300000 /* Pkt Rej. Ena. on both EMAC3 0-1 */
-#define SDR0_MFR_PKT_REJ_EN0		0x00200000 /* Pkt Rej. Enable on EMAC3(0) */
-#define SDR0_MFR_PKT_REJ_EN1		0x00100000 /* Pkt Rej. Enable on EMAC3(1) */
-#define SDR0_MFR_PKT_REJ_POL		0x00080000 /* Packet Reject Polarity */
-
-/* CUST0 Customer Configuration Register0 */
-#define SDR0_CUST0_MUX_E_N_G_MASK	0xC0000000 /* Mux_Emac_NDFC_GPIO */
-#define SDR0_CUST0_MUX_EMAC_SEL		0x40000000 /* Emac Selection */
-#define SDR0_CUST0_MUX_NDFC_SEL		0x80000000 /* NDFC Selection */
-#define SDR0_CUST0_MUX_GPIO_SEL		0xC0000000 /* GPIO Selection */
-
-#define SDR0_CUST0_NDFC_EN_MASK		0x20000000 /* NDFC Enable Mask */
-#define SDR0_CUST0_NDFC_ENABLE		0x20000000 /* NDFC Enable */
-#define SDR0_CUST0_NDFC_DISABLE		0x00000000 /* NDFC Disable */
-
-#define SDR0_CUST0_NDFC_BW_MASK		0x10000000 /* NDFC Boot Width */
-#define SDR0_CUST0_NDFC_BW_16_BIT	0x10000000 /* NDFC Boot Width = 16 Bit */
-#define SDR0_CUST0_NDFC_BW_8_BIT	0x00000000 /* NDFC Boot Width =  8 Bit */
-
-#define SDR0_CUST0_NDFC_BP_MASK		0x0F000000 /* NDFC Boot Page */
-#define SDR0_CUST0_NDFC_BP_ENCODE(n)	((((u32)(n)) & 0xF) << 24)
-#define SDR0_CUST0_NDFC_BP_DECODE(n)	((((u32)(n)) >> 24) & 0xF)
-
-#define SDR0_CUST0_NDFC_BAC_MASK	0x00C00000 /* NDFC Boot Address Cycle */
-#define SDR0_CUST0_NDFC_BAC_ENCODE(n)	((((u32)(n)) & 0x3) << 22)
-#define SDR0_CUST0_NDFC_BAC_DECODE(n)	((((u32)(n)) >> 22) & 0x3)
-
-#define SDR0_CUST0_NDFC_ARE_MASK	0x00200000 /* NDFC Auto Read Enable */
-#define SDR0_CUST0_NDFC_ARE_ENABLE	0x00200000 /* NDFC Auto Read Enable */
-#define SDR0_CUST0_NDFC_ARE_DISABLE	0x00000000 /* NDFC Auto Read Disable */
-
-#define SDR0_CUST0_NRB_MASK		0x00100000 /* NDFC Ready / Busy */
-#define SDR0_CUST0_NRB_BUSY		0x00100000 /* Busy */
-#define SDR0_CUST0_NRB_READY		0x00000000 /* Ready */
-
-#define SDR0_CUST0_NDRSC_MASK		0x0000FFF0 /* NDFC Device Reset Count Mask */
-#define SDR0_CUST0_NDRSC_ENCODE(n)	((((u32)(n)) & 0xFFF) << 4)
-#define SDR0_CUST0_NDRSC_DECODE(n)	((((u32)(n)) >> 4) & 0xFFF)
-
-#define SDR0_CUST0_CHIPSELGAT_MASK	0x0000000F /* Chip Select Gating Mask */
-#define SDR0_CUST0_CHIPSELGAT_DIS	0x00000000 /* Chip Select Gating Disable */
-#define SDR0_CUST0_CHIPSELGAT_ENALL	0x0000000F /*All Chip Select Gating Enable*/
-#define SDR0_CUST0_CHIPSELGAT_EN0	0x00000008 /* Chip Select0 Gating Enable */
-#define SDR0_CUST0_CHIPSELGAT_EN1	0x00000004 /* Chip Select1 Gating Enable */
-#define SDR0_CUST0_CHIPSELGAT_EN2	0x00000002 /* Chip Select2 Gating Enable */
-#define SDR0_CUST0_CHIPSELGAT_EN3	0x00000001 /* Chip Select3 Gating Enable */
-
-#define SDR0_SRST0_BGO		0x80000000 /* PLB to OPB bridge */
-#define SDR0_SRST0_PLB4		0x40000000 /* PLB4 arbiter */
-#define SDR0_SRST0_EBC		0x20000000 /* External bus controller */
-#define SDR0_SRST0_OPB		0x10000000 /* OPB arbiter */
-#define SDR0_SRST0_UART0	0x08000000 /* Universal asynchronous receiver/
-					      transmitter 0 */
-#define SDR0_SRST0_UART1	0x04000000 /* Universal asynchronous receiver/
-					      transmitter 1 */
-#define SDR0_SRST0_IIC0		0x02000000 /* Inter integrated circuit 0 */
-#define SDR0_SRST0_USB2H	0x01000000 /* USB2.0 Host */
-#define SDR0_SRST0_GPIO		0x00800000 /* General purpose I/O */
-#define SDR0_SRST0_GPT		0x00400000 /* General purpose timer */
-#define SDR0_SRST0_DMC		0x00200000 /* DDR SDRAM memory controller */
-#define SDR0_SRST0_PCI		0x00100000 /* PCI */
-#define SDR0_SRST0_EMAC0	0x00080000 /* Ethernet media access controller 0 */
-#define SDR0_SRST0_EMAC1	0x00040000 /* Ethernet media access controller 1 */
-#define SDR0_SRST0_CPM0		0x00020000 /* Clock and power management */
-#define SDR0_SRST0_ZMII		0x00010000 /* ZMII bridge */
-#define SDR0_SRST0_UIC0		0x00008000 /* Universal interrupt controller 0 */
-#define SDR0_SRST0_UIC1		0x00004000 /* Universal interrupt controller 1 */
-#define SDR0_SRST0_IIC1		0x00002000 /* Inter integrated circuit 1 */
-#define SDR0_SRST0_SCP		0x00001000 /* Serial communications port */
-#define SDR0_SRST0_BGI		0x00000800 /* OPB to PLB bridge */
-#define SDR0_SRST0_DMA		0x00000400 /* Direct memory access controller */
-#define SDR0_SRST0_DMAC		0x00000200 /* DMA channel */
-#define SDR0_SRST0_MAL		0x00000100 /* Media access layer */
-#define SDR0_SRST0_USB2D	0x00000080 /* USB2.0 device */
-#define SDR0_SRST0_GPTR		0x00000040 /* General purpose timer */
-#define SDR0_SRST0_P4P3		0x00000010 /* PLB4 to PLB3 bridge */
-#define SDR0_SRST0_P3P4		0x00000008 /* PLB3 to PLB4 bridge */
-#define SDR0_SRST0_PLB3		0x00000004 /* PLB3 arbiter */
-#define SDR0_SRST0_UART2	0x00000002 /* Universal asynchronous receiver/
-					      transmitter 2 */
-#define SDR0_SRST0_UART3	0x00000001 /* Universal asynchronous receiver/
-					      transmitter 3 */
-
-#define SDR0_SRST1_NDFC		0x80000000 /* Nand flash controller */
-#define SDR0_SRST1_OPBA1	0x40000000 /* OPB Arbiter attached to PLB4 */
-#define SDR0_SRST1_P4OPB0	0x20000000 /* PLB4 to OPB Bridge0 */
-#define SDR0_SRST1_PLB42OPB0	SDR0_SRST1_P4OPB0
-#define SDR0_SRST1_DMA4		0x10000000 /* DMA to PLB4 */
-#define SDR0_SRST1_DMA4CH	0x08000000 /* DMA Channel to PLB4 */
-#define SDR0_SRST1_OPBA2	0x04000000 /* OPB Arbiter attached to PLB4
-					      USB 2.0 Host */
-#define SDR0_SRST1_OPB2PLB40	0x02000000 /* OPB to PLB4 Bridge attached to
-					      USB 2.0 Host */
-#define SDR0_SRST1_PLB42OPB1	0x01000000 /* PLB4 to OPB Bridge attached to
-					      USB 2.0 Host */
-#define SDR0_SRST1_CPM1		0x00800000 /* Clock and Power management 1 */
-#define SDR0_SRST1_UIC2		0x00400000 /* Universal Interrupt Controller 2*/
-#define SDR0_SRST1_CRYP0	0x00200000 /* Security Engine */
-#define SDR0_SRST1_USB20PHY	0x00100000 /* USB 2.0 Phy */
-#define SDR0_SRST1_USB2HUTMI	0x00080000 /* USB 2.0 Host UTMI Interface */
-#define SDR0_SRST1_USB2HPHY	0x00040000 /* USB 2.0 Host Phy Interface */
-#define SDR0_SRST1_SRAM0	0x00020000 /* Internal SRAM Controller */
-#define SDR0_SRST1_RGMII0	0x00010000 /* RGMII Bridge */
-#define SDR0_SRST1_ETHPLL	0x00008000 /* Ethernet PLL */
-#define SDR0_SRST1_FPU 		0x00004000 /* Floating Point Unit */
-#define SDR0_SRST1_KASU0	0x00002000 /* Kasumi Engine */
-
-#define PLLSYS0_ENG_MASK	0x80000000	/* 0 = SysClk, 1 = PLL VCO */
-#define PLLSYS0_SRC_MASK	0x40000000	/* 0 = PLL A, 1 = PLL B */
-#define PLLSYS0_SEL_MASK	0x38000000	/* 0 = PLL, 1 = CPU, 5 = PerClk */
-#define PLLSYS0_TUNE_MASK	0x07fe0000	/* PLL Tune bits */
-#define PLLSYS0_FB_DIV_MASK	0x0001f000	/* Feedback divisor */
-#define PLLSYS0_FWD_DIV_A_MASK	0x00000f00	/* Fwd Div A */
-#define PLLSYS0_FWD_DIV_B_MASK	0x000000e0	/* Fwd Div B */
-#define PLLSYS0_PRI_DIV_B_MASK	0x0000001c	/* PLL Primary Divisor B */
-#define PLLSYS0_OPB_DIV_MASK	0x00000003	/* OPB Divisor */
-
-#define PLLC_ENG_MASK		0x20000000  /* PLL primary forward divisor source */
-#define PLLC_SRC_MASK		0x20000000  /* PLL feedback source   */
-#define PLLD_FBDV_MASK		0x1f000000  /* PLL Feedback Divisor  */
-#define PLLD_FWDVA_MASK		0x000f0000  /* PLL Forward Divisor A */
-#define PLLD_FWDVB_MASK		0x00000700  /* PLL Forward Divisor B */
-#define PLLD_LFBDV_MASK		0x0000003f  /* PLL Local Feedback Divisor */
-
-#define OPBDDV_MASK		0x03000000  /* OPB Clock Divisor Register */
-#define PERDV_MASK		0x07000000  /* Peripheral Clock Divisor */
-#define PRADV_MASK		0x07000000  /* Primary Divisor A */
-#define PRBDV_MASK		0x07000000  /* Primary Divisor B */
-#define SPCID_MASK		0x03000000  /* Sync PCI Divisor  */
-
-/* Strap 1 Register */
-#define PLLSYS1_LF_DIV_MASK	0xfc000000	/* PLL Local Feedback Divisor */
-#define PLLSYS1_PERCLK_DIV_MASK 0x03000000	/* Peripheral Clk Divisor */
-#define PLLSYS1_MAL_DIV_MASK	0x00c00000	/* MAL Clk Divisor */
-#define PLLSYS1_RW_MASK		0x00300000	/* ROM width */
-#define PLLSYS1_EAR_MASK	0x00080000	/* ERAP Address reset vector */
-#define PLLSYS1_PAE_MASK	0x00040000	/* PCI arbitor enable */
-#define PLLSYS1_PCHE_MASK	0x00020000	/* PCI host config enable */
-#define PLLSYS1_PISE_MASK	0x00010000	/* PCI init seq. enable */
-#define PLLSYS1_PCWE_MASK	0x00008000	/* PCI local cpu wait enable */
-#define PLLSYS1_PPIM_MASK	0x00007800	/* PCI inbound map */
-#define PLLSYS1_PR64E_MASK	0x00000400	/* PCI init Req64 enable */
-#define PLLSYS1_PXFS_MASK	0x00000300	/* PCI-X Freq Sel */
-#define PLLSYS1_RSVD_MASK	0x00000080	/* RSVD */
-#define PLLSYS1_PDM_MASK	0x00000040	/* PCI-X Driver Mode */
-#define PLLSYS1_EPS_MASK	0x00000038	/* Ethernet Pin Select */
-#define PLLSYS1_RMII_MASK	0x00000004	/* RMII Mode */
-#define PLLSYS1_TRE_MASK	0x00000002	/* GPIO Trace Enable */
-#define PLLSYS1_NTO1_MASK	0x00000001	/* CPU:PLB N-to-1 ratio */
-
-#define CPR0_ICFG_RLI_MASK	0x80000000
-#define CPR0_ICFG_ICS_MASK	0x00000007
-#define CPR0_SPCID_SPCIDV0_MASK	0x03000000
-#define CPR0_SPCID_SPCIDV0_DIV1	0x01000000
-#define CPR0_SPCID_SPCIDV0_DIV2	0x02000000
-#define CPR0_SPCID_SPCIDV0_DIV3	0x03000000
-#define CPR0_SPCID_SPCIDV0_DIV4	0x00000000
-#define CPR0_PERD_PERDV0_MASK	0x07000000
-
-#define PCI_MMIO_LCR_BASE	(CONFIG_SYS_PCI_BASE + 0x0f400000) /* Real =>
-								      0x0EF400000 */
-
-/* PCI Master Local Configuration Registers */
-#define PCIL0_PMM0LA		(PCI_MMIO_LCR_BASE + 0x00) /* PMM0 Local Address */
-#define PCIL0_PMM0MA		(PCI_MMIO_LCR_BASE + 0x04) /* PMM0 Mask/Attribute */
-#define PCIL0_PMM0PCILA		(PCI_MMIO_LCR_BASE + 0x08) /* PMM0 PCI Low Address */
-#define PCIL0_PMM0PCIHA		(PCI_MMIO_LCR_BASE + 0x0C) /* PMM0 PCI High Address */
-#define PCIL0_PMM1LA		(PCI_MMIO_LCR_BASE + 0x10) /* PMM1 Local Address */
-#define PCIL0_PMM1MA		(PCI_MMIO_LCR_BASE + 0x14) /* PMM1 Mask/Attribute */
-#define PCIL0_PMM1PCILA		(PCI_MMIO_LCR_BASE + 0x18) /* PMM1 PCI Low Address */
-#define PCIL0_PMM1PCIHA		(PCI_MMIO_LCR_BASE + 0x1C) /* PMM1 PCI High Address */
-#define PCIL0_PMM2LA		(PCI_MMIO_LCR_BASE + 0x20) /* PMM2 Local Address */
-#define PCIL0_PMM2MA		(PCI_MMIO_LCR_BASE + 0x24) /* PMM2 Mask/Attribute */
-#define PCIL0_PMM2PCILA		(PCI_MMIO_LCR_BASE + 0x28) /* PMM2 PCI Low Address */
-#define PCIL0_PMM2PCIHA		(PCI_MMIO_LCR_BASE + 0x2C) /* PMM2 PCI High Address */
-
-/* PCI Target Local Configuration Registers */
-#define PCIL0_PTM1MS		(PCI_MMIO_LCR_BASE + 0x30) /* PTM1 Memory Size/
-							      Attribute */
-#define PCIL0_PTM1LA		(PCI_MMIO_LCR_BASE + 0x34) /* PTM1 Local Addr. Reg */
-#define PCIL0_PTM2MS		(PCI_MMIO_LCR_BASE + 0x38) /* PTM2 Memory Size/
-							      Attribute */
-#define PCIL0_PTM2LA		(PCI_MMIO_LCR_BASE + 0x3C) /* PTM2 Local Addr. Reg */
-
-/* 440EPx boot strap options */
-#define BOOT_STRAP_OPTION_A	0x00000000
-#define BOOT_STRAP_OPTION_B	0x00000001
-#define BOOT_STRAP_OPTION_D	0x00000003
-#define BOOT_STRAP_OPTION_E	0x00000004
-
-#endif /* _PPC440EPX_GRX_H_ */
diff --git a/arch/powerpc/include/asm/ppc440gp.h b/arch/powerpc/include/asm/ppc440gp.h
deleted file mode 100644
index 01b66c0..0000000
--- a/arch/powerpc/include/asm/ppc440gp.h
+++ /dev/null
@@ -1,59 +0,0 @@
-/*
- * (C) Copyright 2010
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef _PPC440GP_H_
-#define _PPC440GP_H_
-
-#define CONFIG_SDRAM_PPC4xx_IBM_DDR	/* IBM DDR controller */
-
-/*
- * Some SoC specific registers (not common for all 440 SoC's)
- */
-
-/* Memory mapped register */
-#define CONFIG_SYS_PERIPHERAL_BASE	0xe0000000 /* Internal Peripherals */
-
-#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_PERIPHERAL_BASE + 0x0200)
-#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_PERIPHERAL_BASE + 0x0300)
-
-#define GPIO0_BASE		(CONFIG_SYS_PERIPHERAL_BASE + 0x0700)
-
-#define SDR0_PCI0	0x0300
-
-#define CPC0_STRP1_PAE_MASK		(0x80000000 >> 11)
-#define CPC0_STRP1_PISE_MASK		(0x80000000 >> 13)
-
-#define CNTRL_DCR_BASE	0x0b0
-
-#define CPC0_SYS0	(CNTRL_DCR_BASE + 0x30)	/* System configuration reg 0 */
-#define CPC0_SYS1	(CNTRL_DCR_BASE + 0x31)	/* System configuration reg 1 */
-
-#define CPC0_STRP0	(CNTRL_DCR_BASE + 0x34)	/* Power-on config reg 0 (RO) */
-#define CPC0_STRP1	(CNTRL_DCR_BASE + 0x35)	/* Power-on config reg 1 (RO) */
-
-#define CPC0_GPIO	(CNTRL_DCR_BASE + 0x38)	/* GPIO config reg (440GP) */
-
-#define CPC0_CR0	(CNTRL_DCR_BASE + 0x3b)	/* Control 0 register */
-#define CPC0_CR1	(CNTRL_DCR_BASE + 0x3a)	/* Control 1 register */
-
-#define PLLSYS0_TUNE_MASK	0xffc00000	/* PLL TUNE bits	    */
-#define PLLSYS0_FB_DIV_MASK	0x003c0000	/* Feedback divisor	    */
-#define PLLSYS0_FWD_DIV_A_MASK	0x00038000	/* Forward divisor A	    */
-#define PLLSYS0_FWD_DIV_B_MASK	0x00007000	/* Forward divisor B	    */
-#define PLLSYS0_OPB_DIV_MASK	0x00000c00	/* OPB divisor		    */
-#define PLLSYS0_EPB_DIV_MASK	0x00000300	/* EPB divisor		    */
-#define PLLSYS0_EXTSL_MASK	0x00000080	/* PerClk feedback path	    */
-#define PLLSYS0_RW_MASK		0x00000060	/* ROM width		    */
-#define PLLSYS0_RL_MASK		0x00000010	/* ROM location		    */
-#define PLLSYS0_ZMII_SEL_MASK	0x0000000c	/* ZMII selection	    */
-#define PLLSYS0_BYPASS_MASK	0x00000002	/* Bypass PLL		    */
-#define PLLSYS0_NTO1_MASK	0x00000001	/* CPU:PLB N-to-1 ratio	    */
-
-#define PCIL0_BRDGOPT1		(PCIL0_CFGBASE + 0x0040)
-#define PCIL0_BRDGOPT2		(PCIL0_CFGBASE + 0x0044)
-
-#endif /* _PPC440GP_H_ */
diff --git a/arch/powerpc/include/asm/ppc440gx.h b/arch/powerpc/include/asm/ppc440gx.h
deleted file mode 100644
index 7bd36e8..0000000
--- a/arch/powerpc/include/asm/ppc440gx.h
+++ /dev/null
@@ -1,89 +0,0 @@
-/*
- * (C) Copyright 2010
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef _PPC440GX_H_
-#define _PPC440GX_H_
-
-#define CONFIG_SDRAM_PPC4xx_IBM_DDR	/* IBM DDR controller */
-
-/*
- * Some SoC specific registers (not common for all 440 SoC's)
- */
-
-/* Memory mapped register */
-#define CONFIG_SYS_PERIPHERAL_BASE	0xe0000000 /* Internal Peripherals */
-
-#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_PERIPHERAL_BASE + 0x0200)
-#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_PERIPHERAL_BASE + 0x0300)
-
-#define GPIO0_BASE		(CONFIG_SYS_PERIPHERAL_BASE + 0x0700)
-
-/* SDR's */
-#define SDR0_PCI0	0x0300
-
-#define SDR0_SDSTP2	0x4001
-#define SDR0_SDSTP3	0x4003
-
-#define SDR0_SDSTP1_PAE_MASK		(0x80000000 >> 13)
-#define SDR0_SDSTP1_PISE_MASK		(0x80000000 >> 15)
-
-#define SDR0_PFC1_EPS_DECODE(n)		((((u32)(n)) >> 22) & 0x07)
-#define SDR0_PFC1_CTEMS_MASK		(0x80000000 >> 11)
-#define SDR0_PFC1_CTEMS_EMS		0x00000000
-#define SDR0_PFC1_CTEMS_CPUTRACE	(0x80000000 >> 11)
-
-#define SDR0_MFR_ECS_MASK		0x10000000
-
-#define SDR0_SRST_DMC			0x00200000
-
-#define PLLSYS0_ENG_MASK	0x80000000	/* 0 = SysClk, 1 = PLL VCO */
-#define PLLSYS0_SRC_MASK	0x40000000	/* 0 = PLL A, 1 = PLL B */
-#define PLLSYS0_SEL_MASK	0x38000000	/* 0 = PLL, 1 = CPU, 5 = PerClk */
-#define PLLSYS0_TUNE_MASK	0x07fe0000	/* PLL Tune bits */
-#define PLLSYS0_FB_DIV_MASK	0x0001f000	/* Feedback divisor */
-#define PLLSYS0_FWD_DIV_A_MASK	0x00000f00	/* Fwd Div A */
-#define PLLSYS0_FWD_DIV_B_MASK	0x000000e0	/* Fwd Div B */
-#define PLLSYS0_PRI_DIV_B_MASK	0x0000001c	/* PLL Primary Divisor B */
-#define PLLSYS0_OPB_DIV_MASK	0x00000003	/* OPB Divisor */
-
-#define PLLC_ENG_MASK		0x20000000  /* PLL primary forward divisor source */
-#define PLLC_SRC_MASK		0x20000000  /* PLL feedback source   */
-#define PLLD_FBDV_MASK		0x1f000000  /* PLL Feedback Divisor  */
-#define PLLD_FWDVA_MASK		0x000f0000  /* PLL Forward Divisor A */
-#define PLLD_FWDVB_MASK		0x00000700  /* PLL Forward Divisor B */
-#define PLLD_LFBDV_MASK		0x0000003f  /* PLL Local Feedback Divisor */
-
-#define OPBDDV_MASK		0x03000000  /* OPB Clock Divisor Register */
-#define PERDV_MASK		0x07000000  /* Peripheral Clock Divisor */
-#define PRADV_MASK		0x07000000  /* Primary Divisor A */
-#define PRBDV_MASK		0x07000000  /* Primary Divisor B */
-#define SPCID_MASK		0x03000000  /* Sync PCI Divisor  */
-
-/* Strap 1 Register */
-#define PLLSYS1_LF_DIV_MASK	0xfc000000	/* PLL Local Feedback Divisor */
-#define PLLSYS1_PERCLK_DIV_MASK 0x03000000	/* Peripheral Clk Divisor */
-#define PLLSYS1_MAL_DIV_MASK	0x00c00000	/* MAL Clk Divisor */
-#define PLLSYS1_RW_MASK		0x00300000	/* ROM width */
-#define PLLSYS1_EAR_MASK	0x00080000	/* ERAP Address reset vector */
-#define PLLSYS1_PAE_MASK	0x00040000	/* PCI arbitor enable */
-#define PLLSYS1_PCHE_MASK	0x00020000	/* PCI host config enable */
-#define PLLSYS1_PISE_MASK	0x00010000	/* PCI init seq. enable */
-#define PLLSYS1_PCWE_MASK	0x00008000	/* PCI local cpu wait enable */
-#define PLLSYS1_PPIM_MASK	0x00007800	/* PCI inbound map */
-#define PLLSYS1_PR64E_MASK	0x00000400	/* PCI init Req64 enable */
-#define PLLSYS1_PXFS_MASK	0x00000300	/* PCI-X Freq Sel */
-#define PLLSYS1_RSVD_MASK	0x00000080	/* RSVD */
-#define PLLSYS1_PDM_MASK	0x00000040	/* PCI-X Driver Mode */
-#define PLLSYS1_EPS_MASK	0x00000038	/* Ethernet Pin Select */
-#define PLLSYS1_RMII_MASK	0x00000004	/* RMII Mode */
-#define PLLSYS1_TRE_MASK	0x00000002	/* GPIO Trace Enable */
-#define PLLSYS1_NTO1_MASK	0x00000001	/* CPU:PLB N-to-1 ratio */
-
-#define PCIL0_BRDGOPT1		(PCIL0_CFGBASE + 0x0040)
-#define PCIL0_BRDGOPT2		(PCIL0_CFGBASE + 0x0044)
-
-#endif /* _PPC440GX_H_ */
diff --git a/arch/powerpc/include/asm/ppc440sp.h b/arch/powerpc/include/asm/ppc440sp.h
deleted file mode 100644
index 5c2192e..0000000
--- a/arch/powerpc/include/asm/ppc440sp.h
+++ /dev/null
@@ -1,85 +0,0 @@
-/*
- * (C) Copyright 2010
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef _PPC440SP_H_
-#define _PPC440SP_H_
-
-#define CONFIG_SDRAM_PPC4xx_IBM_DDR2	/* IBM DDR(2) controller */
-
-/*
- * Some SoC specific registers (not common for all 440 SoC's)
- */
-
-/* Memory mapped register */
-#define CONFIG_SYS_PERIPHERAL_BASE	0xf0000000 /* Internal Peripherals */
-
-#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_PERIPHERAL_BASE + 0x0200)
-#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_PERIPHERAL_BASE + 0x0300)
-
-#define GPIO0_BASE		(CONFIG_SYS_PERIPHERAL_BASE + 0x0700)
-
-/* SDR's */
-#define SDR0_PCI0	0x0300
-#define SDR0_SDSTP2	0x0022
-#define SDR0_SDSTP3	0x0023
-
-#define SDR0_SDSTP1_PAE_MASK		(0x80000000 >> 13)
-#define SDR0_SDSTP1_PISE_MASK		(0x80000000 >> 15)
-
-#define SDR0_PFC1_EM_1000		(0x80000000 >> 10)
-
-#define SDR0_MFR_FIXD			(0x80000000 >> 3)	/* Workaround for PCI/DMA */
-
-#define SDR0_SRST0_DMC			0x00200000
-
-#define PLLSYS0_ENG_MASK	0x80000000	/* 0 = SysClk, 1 = PLL VCO */
-#define PLLSYS0_SRC_MASK	0x40000000	/* 0 = PLL A, 1 = PLL B */
-#define PLLSYS0_SEL_MASK	0x38000000	/* 0 = PLL, 1 = CPU, 5 = PerClk */
-#define PLLSYS0_TUNE_MASK	0x07fe0000	/* PLL Tune bits */
-#define PLLSYS0_FB_DIV_MASK	0x0001f000	/* Feedback divisor */
-#define PLLSYS0_FWD_DIV_A_MASK	0x00000f00	/* Fwd Div A */
-#define PLLSYS0_FWD_DIV_B_MASK	0x000000e0	/* Fwd Div B */
-#define PLLSYS0_PRI_DIV_B_MASK	0x0000001c	/* PLL Primary Divisor B */
-#define PLLSYS0_OPB_DIV_MASK	0x00000003	/* OPB Divisor */
-
-#define PLLC_ENG_MASK		0x20000000  /* PLL primary forward divisor source */
-#define PLLC_SRC_MASK		0x20000000  /* PLL feedback source   */
-#define PLLD_FBDV_MASK		0x1f000000  /* PLL Feedback Divisor  */
-#define PLLD_FWDVA_MASK		0x000f0000  /* PLL Forward Divisor A */
-#define PLLD_FWDVB_MASK		0x00000700  /* PLL Forward Divisor B */
-#define PLLD_LFBDV_MASK		0x0000003f  /* PLL Local Feedback Divisor */
-
-#define OPBDDV_MASK		0x03000000  /* OPB Clock Divisor Register */
-#define PERDV_MASK		0x07000000  /* Peripheral Clock Divisor */
-#define PRADV_MASK		0x07000000  /* Primary Divisor A */
-#define PRBDV_MASK		0x07000000  /* Primary Divisor B */
-#define SPCID_MASK		0x03000000  /* Sync PCI Divisor  */
-
-/* Strap 1 Register */
-#define PLLSYS1_LF_DIV_MASK	0xfc000000	/* PLL Local Feedback Divisor */
-#define PLLSYS1_PERCLK_DIV_MASK 0x03000000	/* Peripheral Clk Divisor */
-#define PLLSYS1_MAL_DIV_MASK	0x00c00000	/* MAL Clk Divisor */
-#define PLLSYS1_RW_MASK		0x00300000	/* ROM width */
-#define PLLSYS1_EAR_MASK	0x00080000	/* ERAP Address reset vector */
-#define PLLSYS1_PAE_MASK	0x00040000	/* PCI arbitor enable */
-#define PLLSYS1_PCHE_MASK	0x00020000	/* PCI host config enable */
-#define PLLSYS1_PISE_MASK	0x00010000	/* PCI init seq. enable */
-#define PLLSYS1_PCWE_MASK	0x00008000	/* PCI local cpu wait enable */
-#define PLLSYS1_PPIM_MASK	0x00007800	/* PCI inbound map */
-#define PLLSYS1_PR64E_MASK	0x00000400	/* PCI init Req64 enable */
-#define PLLSYS1_PXFS_MASK	0x00000300	/* PCI-X Freq Sel */
-#define PLLSYS1_RSVD_MASK	0x00000080	/* RSVD */
-#define PLLSYS1_PDM_MASK	0x00000040	/* PCI-X Driver Mode */
-#define PLLSYS1_EPS_MASK	0x00000038	/* Ethernet Pin Select */
-#define PLLSYS1_RMII_MASK	0x00000004	/* RMII Mode */
-#define PLLSYS1_TRE_MASK	0x00000002	/* GPIO Trace Enable */
-#define PLLSYS1_NTO1_MASK	0x00000001	/* CPU:PLB N-to-1 ratio */
-
-#define PCIL0_BRDGOPT1		(PCIL0_CFGBASE + 0x0040)
-#define PCIL0_BRDGOPT2		(PCIL0_CFGBASE + 0x0044)
-
-#endif /* _PPC440SP_H_ */
diff --git a/arch/powerpc/include/asm/ppc440spe.h b/arch/powerpc/include/asm/ppc440spe.h
deleted file mode 100644
index 105dc01..0000000
--- a/arch/powerpc/include/asm/ppc440spe.h
+++ /dev/null
@@ -1,101 +0,0 @@
-/*
- * (C) Copyright 2010
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef _PPC440SPE_H_
-#define _PPC440SPE_H_
-
-#define CONFIG_SDRAM_PPC4xx_IBM_DDR2	/* IBM DDR(2) controller */
-
-/*
- * Some SoC specific registers (not common for all 440 SoC's)
- */
-
-/* Memory mapped register */
-#define CONFIG_SYS_PERIPHERAL_BASE	0xa0000000 /* Internal Peripherals */
-
-#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_PERIPHERAL_BASE + 0x0200)
-#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_PERIPHERAL_BASE + 0x0300)
-
-#define GPIO0_BASE		(CONFIG_SYS_PERIPHERAL_BASE + 0x0700)
-
-/* SDR's */
-#define SDR0_PCI0	0x0300
-#define SDR0_SDSTP2	0x0022
-#define SDR0_SDSTP3	0x0023
-
-#define SDR0_SDSTP1_PAE_MASK		(0x80000000 >> 13)
-#define SDR0_SDSTP1_PISE_MASK		(0x80000000 >> 15)
-#define SDR0_SDSTP1_ERPN_MASK		(0x80000000 >> 12)
-#define SDR0_SDSTP1_ERPN_EBC		0
-#define SDR0_SDSTP1_ERPN_PCI		(0x80000000 >> 12)
-#define SDR0_SDSTP1_EBCW_MASK		(0x80000000 >> 24)
-#define SDR0_SDSTP1_EBCW_8_BITS		0
-#define SDR0_SDSTP1_EBCW_16_BITS	(0x80000000 >> 24)
-
-#define SDR0_PFC1_EM_1000		(0x80000000 >> 10)
-
-#define SDR0_MFR_FIXD			(0x80000000 >> 3)	/* Workaround for PCI/DMA */
-
-#define SDR0_PINSTP_BOOTSTRAP_MASK	0xC0000000  /* Strap Bits */
-#define SDR0_PINSTP_BOOTSTRAP_SETTINGS0	0x00000000  /* Default strap settings 0
-						       (EBC boot) */
-#define SDR0_PINSTP_BOOTSTRAP_SETTINGS1	0x40000000  /* Default strap settings 1
-						       (PCI boot) */
-#define SDR0_PINSTP_BOOTSTRAP_IIC_54_EN	0x80000000  /* Serial Device Enabled -
-						       Addr = 0x54 */
-#define SDR0_PINSTP_BOOTSTRAP_IIC_50_EN	0xC0000000  /* Serial Device Enabled -
-						       Addr = 0x50 */
-
-#define SDR0_SRST0_DMC			0x00200000
-
-#define PLLSYS0_ENG_MASK	0x80000000	/* 0 = SysClk, 1 = PLL VCO */
-#define PLLSYS0_SRC_MASK	0x40000000	/* 0 = PLL A, 1 = PLL B */
-#define PLLSYS0_SEL_MASK	0x38000000	/* 0 = PLL, 1 = CPU, 5 = PerClk */
-#define PLLSYS0_TUNE_MASK	0x07fe0000	/* PLL Tune bits */
-#define PLLSYS0_FB_DIV_MASK	0x0001f000	/* Feedback divisor */
-#define PLLSYS0_FWD_DIV_A_MASK	0x00000f00	/* Fwd Div A */
-#define PLLSYS0_FWD_DIV_B_MASK	0x000000e0	/* Fwd Div B */
-#define PLLSYS0_PRI_DIV_B_MASK	0x0000001c	/* PLL Primary Divisor B */
-#define PLLSYS0_OPB_DIV_MASK	0x00000003	/* OPB Divisor */
-
-#define PLLC_ENG_MASK		0x20000000  /* PLL primary forward divisor source */
-#define PLLC_SRC_MASK		0x20000000  /* PLL feedback source   */
-#define PLLD_FBDV_MASK		0x1f000000  /* PLL Feedback Divisor  */
-#define PLLD_FWDVA_MASK		0x000f0000  /* PLL Forward Divisor A */
-#define PLLD_FWDVB_MASK		0x00000700  /* PLL Forward Divisor B */
-#define PLLD_LFBDV_MASK		0x0000003f  /* PLL Local Feedback Divisor */
-
-#define OPBDDV_MASK		0x03000000  /* OPB Clock Divisor Register */
-#define PERDV_MASK		0x07000000  /* Peripheral Clock Divisor */
-#define PRADV_MASK		0x07000000  /* Primary Divisor A */
-#define PRBDV_MASK		0x07000000  /* Primary Divisor B */
-#define SPCID_MASK		0x03000000  /* Sync PCI Divisor  */
-
-/* Strap 1 Register */
-#define PLLSYS1_LF_DIV_MASK	0xfc000000	/* PLL Local Feedback Divisor */
-#define PLLSYS1_PERCLK_DIV_MASK 0x03000000	/* Peripheral Clk Divisor */
-#define PLLSYS1_MAL_DIV_MASK	0x00c00000	/* MAL Clk Divisor */
-#define PLLSYS1_RW_MASK		0x00300000	/* ROM width */
-#define PLLSYS1_EAR_MASK	0x00080000	/* ERAP Address reset vector */
-#define PLLSYS1_PAE_MASK	0x00040000	/* PCI arbitor enable */
-#define PLLSYS1_PCHE_MASK	0x00020000	/* PCI host config enable */
-#define PLLSYS1_PISE_MASK	0x00010000	/* PCI init seq. enable */
-#define PLLSYS1_PCWE_MASK	0x00008000	/* PCI local cpu wait enable */
-#define PLLSYS1_PPIM_MASK	0x00007800	/* PCI inbound map */
-#define PLLSYS1_PR64E_MASK	0x00000400	/* PCI init Req64 enable */
-#define PLLSYS1_PXFS_MASK	0x00000300	/* PCI-X Freq Sel */
-#define PLLSYS1_RSVD_MASK	0x00000080	/* RSVD */
-#define PLLSYS1_PDM_MASK	0x00000040	/* PCI-X Driver Mode */
-#define PLLSYS1_EPS_MASK	0x00000038	/* Ethernet Pin Select */
-#define PLLSYS1_RMII_MASK	0x00000004	/* RMII Mode */
-#define PLLSYS1_TRE_MASK	0x00000002	/* GPIO Trace Enable */
-#define PLLSYS1_NTO1_MASK	0x00000001	/* CPU:PLB N-to-1 ratio */
-
-#define PCIL0_BRDGOPT1		(PCIL0_CFGBASE + 0x0040)
-#define PCIL0_BRDGOPT2		(PCIL0_CFGBASE + 0x0044)
-
-#endif /* _PPC440SPE_H_ */
diff --git a/arch/powerpc/include/asm/ppc460ex_gt.h b/arch/powerpc/include/asm/ppc460ex_gt.h
deleted file mode 100644
index ea019aa..0000000
--- a/arch/powerpc/include/asm/ppc460ex_gt.h
+++ /dev/null
@@ -1,211 +0,0 @@
-/*
- * (C) Copyright 2010
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef _PPC460EX_GT_H_
-#define _PPC460EX_GT_H_
-
-#define CONFIG_SDRAM_PPC4xx_IBM_DDR2	/* IBM DDR(2) controller */
-
-#define CONFIG_NAND_NDFC
-
-/*
- * Some SoC specific registers
- */
-
-/* Memory mapped registers */
-#define CONFIG_SYS_PERIPHERAL_BASE	0xef600000 /* Internal Peripherals */
-
-#ifndef CONFIG_DM_SERIAL
-#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_PERIPHERAL_BASE + 0x0300)
-#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_PERIPHERAL_BASE + 0x0400)
-#define CONFIG_SYS_NS16550_COM3	(CONFIG_SYS_PERIPHERAL_BASE + 0x0500)
-#define CONFIG_SYS_NS16550_COM4	(CONFIG_SYS_PERIPHERAL_BASE + 0x0600)
-#endif
-
-#define GPIO0_BASE		(CONFIG_SYS_PERIPHERAL_BASE + 0x0b00)
-#define GPIO1_BASE		(CONFIG_SYS_PERIPHERAL_BASE + 0x0c00)
-
-/* DCR */
-#define AHB_TOP			0x00a4
-#define AHB_BOT			0x00a5
-
-/* SDR */
-#define SDR0_PCI0		0x01c0
-#define SDR0_AHB_CFG		0x0370
-#define SDR0_USB2HOST_CFG	0x0371
-#define SDR0_ETH_PLL		0x4102
-#define SDR0_ETH_CFG		0x4103
-#define SDR0_ETH_STS		0x4104
-
-/*
- * Register bits and masks
- */
-#define SDR0_SDSTP1_PAE_MASK		(0x80000000 >> 13)
-#define SDR0_SDSTP1_PISE_MASK		(0x80000000 >> 15)
-
-/* CUST0 Customer Configuration Register0 */
-#define SDR0_CUST0_MUX_E_N_G_MASK	0xC0000000 /* Mux_Emac_NDFC_GPIO */
-#define SDR0_CUST0_MUX_EMAC_SEL		0x40000000 /* Emac Selection */
-#define SDR0_CUST0_MUX_NDFC_SEL		0x80000000 /* NDFC Selection */
-#define SDR0_CUST0_MUX_GPIO_SEL		0xC0000000 /* GPIO Selection */
-
-#define SDR0_CUST0_NDFC_EN_MASK		0x20000000 /* NDFC Enable Mask */
-#define SDR0_CUST0_NDFC_ENABLE		0x20000000 /* NDFC Enable */
-#define SDR0_CUST0_NDFC_DISABLE		0x00000000 /* NDFC Disable */
-
-#define SDR0_CUST0_NDFC_BW_MASK		0x10000000 /* NDFC Boot Width */
-#define SDR0_CUST0_NDFC_BW_16_BIT	0x10000000 /* NDFC Boot Width = 16 Bit */
-#define SDR0_CUST0_NDFC_BW_8_BIT	0x00000000 /* NDFC Boot Width =  8 Bit */
-
-#define SDR0_CUST0_NDFC_BP_MASK		0x0F000000 /* NDFC Boot Page */
-#define SDR0_CUST0_NDFC_BP_ENCODE(n)	((((u32)(n)) & 0xF) << 24)
-#define SDR0_CUST0_NDFC_BP_DECODE(n)	((((u32)(n)) >> 24) & 0xF)
-
-#define SDR0_CUST0_NDFC_BAC_MASK	0x00C00000 /* NDFC Boot Address Cycle */
-#define SDR0_CUST0_NDFC_BAC_ENCODE(n)	((((u32)(n)) & 0x3) << 22)
-#define SDR0_CUST0_NDFC_BAC_DECODE(n)	((((u32)(n)) >> 22) & 0x3)
-
-#define SDR0_CUST0_NDFC_ARE_MASK	0x00200000 /* NDFC Auto Read Enable */
-#define SDR0_CUST0_NDFC_ARE_ENABLE	0x00200000 /* NDFC Auto Read Enable */
-#define SDR0_CUST0_NDFC_ARE_DISABLE	0x00000000 /* NDFC Auto Read Disable */
-
-#define SDR0_CUST0_NRB_MASK		0x00100000 /* NDFC Ready / Busy */
-#define SDR0_CUST0_NRB_BUSY		0x00100000 /* Busy */
-#define SDR0_CUST0_NRB_READY		0x00000000 /* Ready */
-
-#define SDR0_CUST0_NDRSC_MASK		0x0000FFF0 /* NDFC Device Reset Count Mask */
-#define SDR0_CUST0_NDRSC_ENCODE(n)	((((u32)(n)) & 0xFFF) << 4)
-#define SDR0_CUST0_NDRSC_DECODE(n)	((((u32)(n)) >> 4) & 0xFFF)
-
-#define SDR0_CUST0_CHIPSELGAT_MASK	0x0000000F /* Chip Select Gating Mask */
-#define SDR0_CUST0_CHIPSELGAT_DIS	0x00000000 /* Chip Select Gating Disable */
-#define SDR0_CUST0_CHIPSELGAT_ENALL	0x0000000F /*All Chip Select Gating Enable*/
-#define SDR0_CUST0_CHIPSELGAT_EN0	0x00000008 /* Chip Select0 Gating Enable */
-#define SDR0_CUST0_CHIPSELGAT_EN1	0x00000004 /* Chip Select1 Gating Enable */
-#define SDR0_CUST0_CHIPSELGAT_EN2	0x00000002 /* Chip Select2 Gating Enable */
-#define SDR0_CUST0_CHIPSELGAT_EN3	0x00000001 /* Chip Select3 Gating Enable */
-
-/* Ethernet PLL Configuration Register (SDR0_ETH_PLL) */
-#define SDR0_ETH_PLL_PLLLOCK	0x80000000	/* Ethernet PLL lock indication */
-
-/* Ethernet Configuration Register (SDR0_ETH_CFG) */
-#define SDR0_ETH_CFG_SGMII3_LPBK	0x00800000 /*SGMII3 port loopback
-						    enable */
-#define SDR0_ETH_CFG_SGMII2_LPBK	0x00400000 /*SGMII2 port loopback
-						    enable */
-#define SDR0_ETH_CFG_SGMII1_LPBK	0x00200000 /*SGMII1 port loopback
-						    enable */
-#define SDR0_ETH_CFG_SGMII0_LPBK	0x00100000 /*SGMII0 port loopback
-						    enable */
-#define SDR0_ETH_CFG_SGMII_MASK		0x00070000 /*SGMII Mask */
-#define SDR0_ETH_CFG_SGMII2_ENABLE	0x00040000 /*SGMII2 port enable */
-#define SDR0_ETH_CFG_SGMII1_ENABLE	0x00020000 /*SGMII1 port enable */
-#define SDR0_ETH_CFG_SGMII0_ENABLE	0x00010000 /*SGMII0 port enable */
-#define SDR0_ETH_CFG_TAHOE1_BYPASS	0x00002000 /*TAHOE1 Bypass selector */
-#define SDR0_ETH_CFG_TAHOE0_BYPASS	0x00001000 /*TAHOE0 Bypass selector */
-#define SDR0_ETH_CFG_EMAC3_PHY_CLK_SEL	0x00000800 /*EMAC 3 PHY clock selector*/
-#define SDR0_ETH_CFG_EMAC2_PHY_CLK_SEL	0x00000400 /*EMAC 2 PHY clock selector*/
-#define SDR0_ETH_CFG_EMAC1_PHY_CLK_SEL	0x00000200 /*EMAC 1 PHY clock selector*/
-#define SDR0_ETH_CFG_EMAC0_PHY_CLK_SEL	0x00000100 /*EMAC 0 PHY clock selector*/
-#define SDR0_ETH_CFG_EMAC_2_1_SWAP	0x00000080 /*Swap EMAC2 with EMAC1 */
-#define SDR0_ETH_CFG_EMAC_0_3_SWAP	0x00000040 /*Swap EMAC0 with EMAC3 */
-#define SDR0_ETH_CFG_MDIO_SEL_MASK	0x00000030 /*MDIO source selector mask*/
-#define SDR0_ETH_CFG_MDIO_SEL_EMAC0	0x00000000 /*MDIO source - EMAC0 */
-#define SDR0_ETH_CFG_MDIO_SEL_EMAC1	0x00000010 /*MDIO source - EMAC1 */
-#define SDR0_ETH_CFG_MDIO_SEL_EMAC2	0x00000020 /*MDIO source - EMAC2 */
-#define SDR0_ETH_CFG_MDIO_SEL_EMAC3	0x00000030 /*MDIO source - EMAC3 */
-#define SDR0_ETH_CFG_GMC1_BRIDGE_SEL	0x00000002 /*GMC Port 1 bridge
-						     selector */
-#define SDR0_ETH_CFG_GMC0_BRIDGE_SEL	0x00000001 /*GMC Port 0 bridge
-						    selector */
-
-#define SDR0_SRST0_BGO		0x80000000 /* PLB to OPB bridge */
-#define SDR0_SRST0_PLB4		0x40000000 /* PLB4 arbiter */
-#define SDR0_SRST0_EBC		0x20000000 /* External bus controller */
-#define SDR0_SRST0_OPB		0x10000000 /* OPB arbiter */
-#define SDR0_SRST0_UART0	0x08000000 /* Universal asynchronous receiver/
-					      transmitter 0 */
-#define SDR0_SRST0_UART1	0x04000000 /* Universal asynchronous receiver/
-					      transmitter 1 */
-#define SDR0_SRST0_IIC0		0x02000000 /* Inter integrated circuit 0 */
-#define SDR0_SRST0_IIC1		0x01000000 /* Inter integrated circuit 1 */
-#define SDR0_SRST0_GPIO0	0x00800000 /* General purpose I/O 0 */
-#define SDR0_SRST0_GPT		0x00400000 /* General purpose timer */
-#define SDR0_SRST0_DMC		0x00200000 /* DDR SDRAM memory controller */
-#define SDR0_SRST0_PCI		0x00100000 /* PCI */
-#define SDR0_SRST0_CPM0		0x00020000 /* Clock and power management */
-#define SDR0_SRST0_IMU		0x00010000 /* I2O DMA */
-#define SDR0_SRST0_UIC0		0x00008000 /* Universal interrupt controller 0*/
-#define SDR0_SRST0_UIC1		0x00004000 /* Universal interrupt controller 1*/
-#define SDR0_SRST0_SRAM		0x00002000 /* Universal interrupt controller 0*/
-#define SDR0_SRST0_UIC2		0x00001000 /* Universal interrupt controller 2*/
-#define SDR0_SRST0_UIC3		0x00000800 /* Universal interrupt controller 3*/
-#define SDR0_SRST0_OCM		0x00000400 /* Universal interrupt controller 0*/
-#define SDR0_SRST0_UART2	0x00000200 /* Universal asynchronous receiver/
-					      transmitter 2 */
-#define SDR0_SRST0_MAL		0x00000100 /* Media access layer */
-#define SDR0_SRST0_GPTR         0x00000040 /* General purpose timer */
-#define SDR0_SRST0_L2CACHE	0x00000004 /* L2 Cache */
-#define SDR0_SRST0_UART3	0x00000002 /* Universal asynchronous receiver/
-					      transmitter 3 */
-#define SDR0_SRST0_GPIO1	0x00000001 /* General purpose I/O 1 */
-
-#define SDR0_SRST1_RLL		0x80000000 /* SRIO RLL */
-#define SDR0_SRST1_SCP		0x40000000 /* Serial communications port */
-#define SDR0_SRST1_PLBARB	0x20000000 /* PLB Arbiter */
-#define SDR0_SRST1_EIPPKP	0x10000000 /* EIPPPKP */
-#define SDR0_SRST1_EIP94	0x08000000 /* EIP 94 */
-#define SDR0_SRST1_EMAC0	0x04000000 /* Ethernet media access
-					      controller 0 */
-#define SDR0_SRST1_EMAC1	0x02000000 /* Ethernet media access
-					      controller 1 */
-#define SDR0_SRST1_EMAC2	0x01000000 /* Ethernet media access
-					      controller 2 */
-#define SDR0_SRST1_EMAC3	0x00800000 /* Ethernet media access
-					      controller 3 */
-#define SDR0_SRST1_ZMII		0x00400000 /* Ethernet ZMII/RMII/SMII */
-#define SDR0_SRST1_RGMII0	0x00200000 /* Ethernet RGMII/RTBI 0 */
-#define SDR0_SRST1_RGMII1	0x00100000 /* Ethernet RGMII/RTBI 1 */
-#define SDR0_SRST1_DMA4		0x00080000 /* DMA to PLB4 */
-#define SDR0_SRST1_DMA4CH	0x00040000 /* DMA Channel to PLB4 */
-#define SDR0_SRST1_SATAPHY	0x00020000 /* Serial ATA PHY */
-#define SDR0_SRST1_SRIODEV	0x00010000 /* Serial Rapid IO core, PCS, and
-					      serdes */
-#define SDR0_SRST1_SRIOPCS	0x00008000 /* Serial Rapid IO core and PCS */
-#define SDR0_SRST1_NDFC		0x00004000 /* Nand flash controller */
-#define SDR0_SRST1_SRIOPLB	0x00002000 /* Serial Rapid IO PLB */
-#define SDR0_SRST1_ETHPLL	0x00001000 /* Ethernet PLL */
-#define SDR0_SRST1_TAHOE1	0x00000800 /* Ethernet Tahoe 1 */
-#define SDR0_SRST1_TAHOE0	0x00000400 /* Ethernet Tahoe 0 */
-#define SDR0_SRST1_SGMII0	0x00000200 /* Ethernet SGMII 0 */
-#define SDR0_SRST1_SGMII1	0x00000100 /* Ethernet SGMII 1 */
-#define SDR0_SRST1_SGMII2	0x00000080 /* Ethernet SGMII 2 */
-#define SDR0_SRST1_AHB		0x00000040 /* PLB4XAHB bridge */
-#define SDR0_SRST1_USBOTGPHY	0x00000020 /* USB 2.0 OTG PHY */
-#define SDR0_SRST1_USBOTG	0x00000010 /* USB 2.0 OTG controller */
-#define SDR0_SRST1_USBHOST	0x00000008 /* USB 2.0 Host controller */
-#define SDR0_SRST1_AHBDMAC	0x00000004 /* AHB DMA controller */
-#define SDR0_SRST1_AHBICM	0x00000002 /* AHB inter-connect matrix */
-#define SDR0_SRST1_SATA		0x00000001 /* Serial ATA controller */
-
-#define PLLSYS0_FWD_DIV_A_MASK	0x000000f0	/* Fwd Div A */
-#define PLLSYS0_FWD_DIV_B_MASK	0x0000000f	/* Fwd Div B */
-#define PLLSYS0_FB_DIV_MASK	0x0000ff00	/* Feedback divisor */
-#define PLLSYS0_OPB_DIV_MASK	0x0c000000	/* OPB Divisor */
-#define PLLSYS0_PLBEDV0_DIV_MASK 0xe0000000	/* PLB Early Clock Divisor */
-#define PLLSYS0_PERCLK_DIV_MASK 0x03000000	/* Peripheral Clk Divisor */
-#define PLLSYS0_SEL_MASK	0x18000000	/* 0 = PLL, 1 = PerClk */
-
-#define CPR0_ICFG_RLI_MASK	0x80000000
-
-#define CPR0_PLLC_RST		0x80000000
-#define CPR0_PLLC_ENG		0x40000000
-
-#define PCIL0_BRDGOPT1		(PCIL0_CFGBASE + 0x0040)
-#define PCIL0_BRDGOPT2		(PCIL0_CFGBASE + 0x0044)
-
-#endif /* _PPC460EX_GT_H_ */
diff --git a/arch/powerpc/include/asm/ppc460sx.h b/arch/powerpc/include/asm/ppc460sx.h
deleted file mode 100644
index b692d07..0000000
--- a/arch/powerpc/include/asm/ppc460sx.h
+++ /dev/null
@@ -1,31 +0,0 @@
-/*
- * (C) Copyright 2010
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef _PPC460SX_H_
-#define _PPC460SX_H_
-
-#define CONFIG_SDRAM_PPC4xx_IBM_DDR2	/* IBM DDR(2) controller */
-
-/* Memory mapped registers */
-#define CONFIG_SYS_PERIPHERAL_BASE	0xa0000000 /* Internal Peripherals */
-
-#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_PERIPHERAL_BASE + 0x0200)
-#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_PERIPHERAL_BASE + 0x0300)
-
-#define GPIO0_BASE		(CONFIG_SYS_PERIPHERAL_BASE + 0x0700)
-
-#define SDR0_SRST0_DMC			0x00200000
-
-#define PLLSYS0_FWD_DIV_A_MASK	0x000000f0	/* Fwd Div A */
-#define PLLSYS0_FWD_DIV_B_MASK	0x0000000f	/* Fwd Div B */
-#define PLLSYS0_FB_DIV_MASK	0x0000ff00	/* Feedback divisor */
-#define PLLSYS0_OPB_DIV_MASK	0x0c000000	/* OPB Divisor */
-#define PLLSYS0_PLBEDV0_DIV_MASK 0xe0000000	/* PLB Early Clock Divisor */
-#define PLLSYS0_PERCLK_DIV_MASK 0x03000000	/* Peripheral Clk Divisor */
-#define PLLSYS0_SEL_MASK	0x18000000	/* 0 = PLL, 1 = PerClk */
-
-#endif /* _PPC460SX_H_ */
diff --git a/arch/powerpc/include/asm/ppc4xx-ebc.h b/arch/powerpc/include/asm/ppc4xx-ebc.h
deleted file mode 100644
index 952783f..0000000
--- a/arch/powerpc/include/asm/ppc4xx-ebc.h
+++ /dev/null
@@ -1,183 +0,0 @@
-/*
- * (C) Copyright 2008
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef _PPC4xx_EBC_H_
-#define _PPC4xx_EBC_H_
-
-/*
- * Currently there are two register layout versions for the IBM EBC core
- * used on 4xx PPC's. The following grouping lists the first layout.
- * Within this group there is a slight variation concerning the bit field
- * position of the EMPL and EMPH fields:
- */
-#if defined(CONFIG_405GP) || \
-    defined(CONFIG_405EP) || \
-    defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
-    defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
-#define CONFIG_EBC_PPC4xx_IBM_VER1
-#if defined(CONFIG_405GP) || \
-    defined(CONFIG_405EP)
-#define EBC_CFG_EMPH_POS	8
-#define EBC_CFG_EMPL_POS	6
-#else
-#define EBC_CFG_EMPH_POS	6
-#define EBC_CFG_EMPL_POS	8
-#endif
-#endif
-
-/*
- * Define the max number of EBC banks (chip selects)
- */
-#if defined(CONFIG_405GP) || \
-    defined(CONFIG_405EZ) || \
-    defined(CONFIG_440GP) || defined(CONFIG_440GX)
-#define EBC_NUM_BANKS	8
-#endif
-
-#if defined(CONFIG_405EP)
-#define EBC_NUM_BANKS	5
-#endif
-
-#if defined(CONFIG_405EX) || \
-    defined(CONFIG_460SX)
-#define EBC_NUM_BANKS	4
-#endif
-
-#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
-    defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
-    defined(CONFIG_460EX) || defined(CONFIG_460GT)
-#define EBC_NUM_BANKS	6
-#endif
-
-#if defined(CONFIG_440SP) || defined(CONFIG_440SPE)
-#define EBC_NUM_BANKS	3
-#endif
-
-/* Bank Configuration Register */
-#define EBC_BXCR(n)		(n)
-#define EBC_BXCR_BANK_SIZE(n)	(0x100000 << (((n) & EBC_BXCR_BS_MASK) >> 17))
-
-#define	EBC_BXCR_BAS_MASK	PPC_REG_VAL(11, 0xFFF)
-#define EBC_BXCR_BAS_ENCODE(n)	(((static_cast(u32, n)) & EBC_BXCR_BAS_MASK))
-#define EBC_BXCR_BS_MASK	PPC_REG_VAL(14, 0x7)
-#define EBC_BXCR_BS_1MB		PPC_REG_VAL(14, 0x0)
-#define EBC_BXCR_BS_2MB		PPC_REG_VAL(14, 0x1)
-#define EBC_BXCR_BS_4MB		PPC_REG_VAL(14, 0x2)
-#define EBC_BXCR_BS_8MB		PPC_REG_VAL(14, 0x3)
-#define EBC_BXCR_BS_16MB	PPC_REG_VAL(14, 0x4)
-#define EBC_BXCR_BS_32MB	PPC_REG_VAL(14, 0x5)
-#define EBC_BXCR_BS_64MB	PPC_REG_VAL(14, 0x6)
-#define EBC_BXCR_BS_128MB	PPC_REG_VAL(14, 0x7)
-#define EBC_BXCR_BU_MASK	PPC_REG_VAL(16, 0x3)
-#define	EBC_BXCR_BU_NONE	PPC_REG_VAL(16, 0x0)
-#define EBC_BXCR_BU_R		PPC_REG_VAL(16, 0x1)
-#define EBC_BXCR_BU_W		PPC_REG_VAL(16, 0x2)
-#define EBC_BXCR_BU_RW		PPC_REG_VAL(16, 0x3)
-#define EBC_BXCR_BW_MASK	PPC_REG_VAL(18, 0x3)
-#define EBC_BXCR_BW_8BIT	PPC_REG_VAL(18, 0x0)
-#define EBC_BXCR_BW_16BIT	PPC_REG_VAL(18, 0x1)
-#if defined(CONFIG_EBC_PPC4xx_IBM_VER1)
-#define EBC_BXCR_BW_32BIT	PPC_REG_VAL(18, 0x2)
-#else
-#define EBC_BXCR_BW_32BIT	PPC_REG_VAL(18, 0x3)
-#endif
-
-/* Bank Access Parameter Register */
-#define EBC_BXAP_BME_ENABLED	PPC_REG_VAL(0, 0x1)
-#define EBC_BXAP_BME_DISABLED	PPC_REG_VAL(0, 0x0)
-#define EBC_BXAP_TWT_ENCODE(n)	PPC_REG_VAL(8, (static_cast(u32, n)) & 0xFF)
-#define	EBC_BXAP_FWT_ENCODE(n)	PPC_REG_VAL(5, (static_cast(u32, n)) & 0x1F)
-#define	EBC_BXAP_BWT_ENCODE(n)	PPC_REG_VAL(8, (static_cast(u32, n)) & 0x7)
-#define EBC_BXAP_BCE_DISABLE	PPC_REG_VAL(9, 0x0)
-#define EBC_BXAP_BCE_ENABLE	PPC_REG_VAL(9, 0x1)
-#define EBC_BXAP_BCT_MASK	PPC_REG_VAL(11, 0x3)
-#define EBC_BXAP_BCT_2TRANS	PPC_REG_VAL(11, 0x0)
-#define EBC_BXAP_BCT_4TRANS	PPC_REG_VAL(11, 0x1)
-#define EBC_BXAP_BCT_8TRANS	PPC_REG_VAL(11, 0x2)
-#define EBC_BXAP_BCT_16TRANS	PPC_REG_VAL(11, 0x3)
-#define EBC_BXAP_CSN_ENCODE(n)	PPC_REG_VAL(13, (static_cast(u32, n)) & 0x3)
-#define EBC_BXAP_OEN_ENCODE(n)	PPC_REG_VAL(15, (static_cast(u32, n)) & 0x3)
-#define EBC_BXAP_WBN_ENCODE(n)	PPC_REG_VAL(17, (static_cast(u32, n)) & 0x3)
-#define EBC_BXAP_WBF_ENCODE(n)	PPC_REG_VAL(19, (static_cast(u32, n)) & 0x3)
-#define EBC_BXAP_TH_ENCODE(n)	PPC_REG_VAL(22, (static_cast(u32, n)) & 0x7)
-#define EBC_BXAP_RE_ENABLED	PPC_REG_VAL(23, 0x1)
-#define EBC_BXAP_RE_DISABLED	PPC_REG_VAL(23, 0x0)
-#define EBC_BXAP_SOR_DELAYED	PPC_REG_VAL(24, 0x0)
-#define EBC_BXAP_SOR_NONDELAYED	PPC_REG_VAL(24, 0x1)
-#define EBC_BXAP_BEM_WRITEONLY	PPC_REG_VAL(25, 0x0)
-#define EBC_BXAP_BEM_RW		PPC_REG_VAL(25, 0x1)
-#define EBC_BXAP_PEN_DISABLED	PPC_REG_VAL(26, 0x0)
-#define EBC_BXAP_PEN_ENABLED	PPC_REG_VAL(26, 0x1)
-
-/* Common fields in EBC0_CFG register */
-#define EBC_CFG_PTD_MASK	PPC_REG_VAL(1, 0x1)
-#define EBC_CFG_PTD_ENABLE	PPC_REG_VAL(1, 0x0)
-#define EBC_CFG_PTD_DISABLE	PPC_REG_VAL(1, 0x1)
-#define EBC_CFG_RTC_MASK	PPC_REG_VAL(4, 0x7)
-#define EBC_CFG_RTC_16PERCLK	PPC_REG_VAL(4, 0x0)
-#define EBC_CFG_RTC_32PERCLK	PPC_REG_VAL(4, 0x1)
-#define EBC_CFG_RTC_64PERCLK	PPC_REG_VAL(4, 0x2)
-#define EBC_CFG_RTC_128PERCLK	PPC_REG_VAL(4, 0x3)
-#define EBC_CFG_RTC_256PERCLK	PPC_REG_VAL(4, 0x4)
-#define EBC_CFG_RTC_512PERCLK	PPC_REG_VAL(4, 0x5)
-#define EBC_CFG_RTC_1024PERCLK	PPC_REG_VAL(4, 0x6)
-#define EBC_CFG_RTC_2048PERCLK	PPC_REG_VAL(4, 0x7)
-#define EBC_CFG_PME_MASK	PPC_REG_VAL(14, 0x1)
-#define EBC_CFG_PME_DISABLE	PPC_REG_VAL(14, 0x0)
-#define EBC_CFG_PME_ENABLE	PPC_REG_VAL(14, 0x1)
-#define EBC_CFG_PMT_MASK	PPC_REG_VAL(19, 0x1F)
-#define EBC_CFG_PMT_ENCODE(n)	PPC_REG_VAL(19, (static_cast(u32, n)) & 0x1F)
-
-/* Now the two versions of the other bits */
-#if defined(CONFIG_EBC_PPC4xx_IBM_VER1)
-#define EBC_CFG_EBTC_MASK	PPC_REG_VAL(0, 0x1)
-#define EBC_CFG_EBTC_HI		PPC_REG_VAL(0, 0x0)
-#define EBC_CFG_EBTC_DRIVEN	PPC_REG_VAL(0, 0x1)
-#define EBC_CFG_EMPH_MASK	PPC_REG_VAL(EBC_CFG_EMPH_POS, 0x3)
-#define EBC_CFG_EMPH_ENCODE(n)	PPC_REG_VAL(EBC_CFG_EMPH_POS, \
-						(static_cast(u32, n)) & 0x3)
-#define EBC_CFG_EMPL_MASK	PPC_REG_VAL(EBC_CFG_EMPL_POS, 0x3)
-#define EBC_CFG_EMPL_ENCODE(n)	PPC_REG_VAL(EBC_CFG_EMPH_POS, \
-						(static_cast(u32, n)) & 0x3)
-#define EBC_CFG_CSTC_MASK	PPC_REG_VAL(9, 0x1)
-#define EBC_CFG_CSTC_HI		PPC_REG_VAL(9, 0x0)
-#define EBC_CFG_CSTC_DRIVEN	PPC_REG_VAL(9, 0x1)
-#define EBC_CFG_BPR_MASK	PPC_REG_VAL(11, 0x3)
-#define EBC_CFG_BPR_1DW		PPC_REG_VAL(11, 0x0)
-#define EBC_CFG_BPR_2DW		PPC_REG_VAL(11, 0x1)
-#define EBC_CFG_BPR_4DW		PPC_REG_VAL(11, 0x2)
-#define EBC_CFG_EMS_MASK	PPC_REG_VAL(13, 0x3)
-#define EBC_CFG_EMS_8BIT	PPC_REG_VAL(13, 0x0)
-#define EBC_CFG_EMS_16BIT	PPC_REG_VAL(13, 0x1)
-#define EBC_CFG_EMS_32BIT	PPC_REG_VAL(13, 0x2)
-#else
-#define EBC_CFG_LE_MASK		PPC_REG_VAL(0, 0x1)
-#define EBC_CFG_LE_UNLOCK	PPC_REG_VAL(0, 0x0)
-#define EBC_CFG_LE_LOCK		PPC_REG_VAL(0, 0x1)
-#define EBC_CFG_ATC_MASK	PPC_REG_VAL(5, 0x1)
-#define EBC_CFG_ATC_HI		PPC_REG_VAL(5, 0x0)
-#define EBC_CFG_ATC_PREVIOUS	PPC_REG_VAL(5, 0x1)
-#define EBC_CFG_DTC_MASK	PPC_REG_VAL(6, 0x1)
-#define EBC_CFG_DTC_HI		PPC_REG_VAL(6, 0x0)
-#define EBC_CFG_DTC_PREVIOUS	PPC_REG_VAL(6, 0x1)
-#define EBC_CFG_CTC_MASK	PPC_REG_VAL(7, 0x1)
-#define EBC_CFG_CTC_HI		PPC_REG_VAL(7, 0x0)
-#define EBC_CFG_CTC_PREVIOUS	PPC_REG_VAL(7, 0x1)
-#define EBC_CFG_OEO_MASK	PPC_REG_VAL(8, 0x1)
-#define EBC_CFG_OEO_HI		PPC_REG_VAL(8, 0x0)
-#define EBC_CFG_OEO_PREVIOUS	PPC_REG_VAL(8, 0x1)
-#define EBC_CFG_EMC_MASK	PPC_REG_VAL(9, 0x1)
-#define EBC_CFG_EMC_NONDEFAULT	PPC_REG_VAL(9, 0x0)
-#define EBC_CFG_EMC_DEFAULT	PPC_REG_VAL(9, 0x1)
-#define EBC_CFG_PR_MASK		PPC_REG_VAL(21, 0x3)
-#define EBC_CFG_PR_16		PPC_REG_VAL(21, 0x0)
-#define EBC_CFG_PR_32		PPC_REG_VAL(21, 0x1)
-#define EBC_CFG_PR_64		PPC_REG_VAL(21, 0x2)
-#define EBC_CFG_PR_128		PPC_REG_VAL(21, 0x3)
-#endif
-
-#endif /* _PPC4xx_EBC_H_ */
diff --git a/arch/powerpc/include/asm/ppc4xx-emac.h b/arch/powerpc/include/asm/ppc4xx-emac.h
deleted file mode 100644
index 76fa95c..0000000
--- a/arch/powerpc/include/asm/ppc4xx-emac.h
+++ /dev/null
@@ -1,536 +0,0 @@
-/*
- * SPDX-License-Identifier:	GPL-2.0	IBM-pibs
- */
-/*----------------------------------------------------------------------------+
-|
-|  File Name:	enetemac.h
-|
-|  Function:	Header file for the EMAC3 macro on the 405GP.
-|
-|  Author:	Mark Wisner
-|
-|  Change Activity-
-|
-|  Date	       Description of Change					   BY
-|  ---------   ---------------------					   ---
-|  29-Apr-99   Created							   MKW
-|
-+----------------------------------------------------------------------------*/
-/*----------------------------------------------------------------------------+
-|  19-Nov-03   Travis Sawyer, Sandburst Corporation, tsawyer@sandburst.com
-|	       ported to handle 440GP and 440GX multiple EMACs
-+----------------------------------------------------------------------------*/
-
-#ifndef _PPC4XX_ENET_H_
-#define _PPC4XX_ENET_H_
-
-#include <net.h>
-#include "asm/ppc4xx-mal.h"
-
-
-/*-----------------------------------------------------------------------------+
-| General enternet defines.  802 frames are not supported.
-+-----------------------------------------------------------------------------*/
-#define ENET_ADDR_LENGTH		6
-#define ENET_ARPTYPE			0x806
-#define ARP_REQUEST			1
-#define ARP_REPLY			2
-#define ENET_IPTYPE			0x800
-#define ARP_CACHE_SIZE			5
-
-#define NUM_TX_BUFF 1
-#define NUM_RX_BUFF PKTBUFSRX
-
-struct enet_frame {
-   unsigned char	dest_addr[ENET_ADDR_LENGTH];
-   unsigned char	source_addr[ENET_ADDR_LENGTH];
-   unsigned short	type;
-   unsigned char	enet_data[1];
-};
-
-struct arp_entry {
-   unsigned long	inet_address;
-   unsigned char	mac_address[ENET_ADDR_LENGTH];
-   unsigned long	valid;
-   unsigned long	sec;
-   unsigned long	nsec;
-};
-
-
-/* Statistic Areas */
-#define MAX_ERR_LOG 10
-
-typedef struct emac_stats_st{	/* Statistic Block */
-	int data_len_err;
-	int rx_frames;
-	int rx;
-	int rx_prot_err;
-	int int_err;
-	int pkts_tx;
-	int pkts_rx;
-	int pkts_handled;
-	short tx_err_log[MAX_ERR_LOG];
-	short rx_err_log[MAX_ERR_LOG];
-} EMAC_STATS_ST, *EMAC_STATS_PST;
-
-/* Structure containing variables used by the shared code (4xx_enet.c) */
-typedef struct emac_4xx_hw_st {
-    uint32_t		hw_addr;		/* EMAC offset */
-    uint32_t		tah_addr;		/* TAH offset */
-    uint32_t		phy_id;
-    uint32_t		phy_addr;
-    uint32_t		original_fc;
-    uint32_t		txcw;
-    uint32_t		autoneg_failed;
-    uint32_t		emac_ier;
-    volatile mal_desc_t *tx;
-    volatile mal_desc_t *rx;
-    u32			tx_phys;
-    u32			rx_phys;
-    bd_t		*bis;	/* for eth_init upon mal error */
-    mal_desc_t		*alloc_tx_buf;
-    mal_desc_t		*alloc_rx_buf;
-    char		*txbuf_ptr;
-    uint16_t		devnum;
-    int			get_link_status;
-    int			tbi_compatibility_en;
-    int			tbi_compatibility_on;
-    int			fc_send_xon;
-    int			report_tx_early;
-    int			first_init;
-    int			tx_err_index;
-    int			rx_err_index;
-    int			rx_slot;	/* MAL Receive Slot */
-    int			rx_i_index;	/* Receive Interrupt Queue Index */
-    int			rx_u_index;	/* Receive User Queue Index */
-    int			tx_slot;	/* MAL Transmit Slot */
-    int			tx_i_index;	/* Transmit Interrupt Queue Index */
-    int			tx_u_index;		/* Transmit User Queue Index */
-    int			rx_ready[NUM_RX_BUFF];	/* Receive Ready Queue */
-    int			tx_run[NUM_TX_BUFF];	/* Transmit Running Queue */
-    int			is_receiving;	/* sync with eth interrupt */
-    int			print_speed;	/* print speed message upon start */
-    EMAC_STATS_ST	stats;
-} EMAC_4XX_HW_ST, *EMAC_4XX_HW_PST;
-
-
-#if defined(CONFIG_440GX) || defined(CONFIG_460GT)
-#define EMAC_NUM_DEV		4
-#elif (defined(CONFIG_440) || defined(CONFIG_405EP)) &&	\
-	!defined(CONFIG_440SP) && !defined(CONFIG_440SPE)
-#define EMAC_NUM_DEV		2
-#else
-#define EMAC_NUM_DEV		1
-#endif
-
-#ifdef CONFIG_IBM_EMAC4_V4	/* EMAC4 V4 changed bit setting */
-#define EMAC_STACR_OC_MASK	(0x00008000)
-#else
-#define EMAC_STACR_OC_MASK	(0x00000000)
-#endif
-
-/*
- * XMII bridge configurations for those systems (e.g. 405EX(r)) that do
- * not have a pin function control (PFC) register to otherwise determine
- * the bridge configuration.
- */
-#define EMAC_PHY_MODE_NONE		0
-#define EMAC_PHY_MODE_NONE_RGMII	1
-#define EMAC_PHY_MODE_RGMII_NONE	2
-#define EMAC_PHY_MODE_RGMII_RGMII	3
-#define EMAC_PHY_MODE_NONE_GMII		4
-#define EMAC_PHY_MODE_GMII_NONE		5
-#define EMAC_PHY_MODE_NONE_MII		6
-#define EMAC_PHY_MODE_MII_NONE		7
-
-/* ZMII Bridge Register addresses */
-#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
-    defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
-    defined(CONFIG_460EX) || defined(CONFIG_460GT)
-#define ZMII0_BASE		(CONFIG_SYS_PERIPHERAL_BASE + 0x0D00)
-#else
-#define ZMII0_BASE		(CONFIG_SYS_PERIPHERAL_BASE + 0x0780)
-#endif
-#define ZMII0_FER		(ZMII0_BASE)
-#define ZMII0_SSR		(ZMII0_BASE + 4)
-#define ZMII0_SMIISR		(ZMII0_BASE + 8)
-
-/* ZMII FER Register Bit Definitions */
-#define ZMII_FER_DIS		(0x0)
-#define ZMII_FER_MDI		(0x8)
-#define ZMII_FER_SMII		(0x4)
-#define ZMII_FER_RMII		(0x2)
-#define ZMII_FER_MII		(0x1)
-
-#define ZMII_FER_RSVD11		(0x00200000)
-#define ZMII_FER_RSVD10		(0x00100000)
-#define ZMII_FER_RSVD14_31	(0x0003FFFF)
-
-#define ZMII_FER_V(__x)		(((3 - __x) * 4) + 16)
-
-
-/* ZMII Speed Selection Register Bit Definitions */
-#define ZMII0_SSR_SCI		(0x4)
-#define ZMII0_SSR_FSS		(0x2)
-#define ZMII0_SSR_SP		(0x1)
-#define ZMII0_SSR_RSVD16_31	(0x0000FFFF)
-
-#define ZMII0_SSR_V(__x)		(((3 - __x) * 4) + 16)
-
-
-/* ZMII SMII Status Register Bit Definitions */
-#define ZMII0_SMIISR_E1		(0x80)
-#define ZMII0_SMIISR_EC		(0x40)
-#define ZMII0_SMIISR_EN		(0x20)
-#define ZMII0_SMIISR_EJ		(0x10)
-#define ZMII0_SMIISR_EL		(0x08)
-#define ZMII0_SMIISR_ED		(0x04)
-#define ZMII0_SMIISR_ES		(0x02)
-#define ZMII0_SMIISR_EF		(0x01)
-
-#define ZMII0_SMIISR_V(__x)	((3 - __x) * 8)
-
-/* RGMII Register Addresses */
-#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
-#define RGMII_BASE		(CONFIG_SYS_PERIPHERAL_BASE + 0x1000)
-#elif defined(CONFIG_460EX) || defined(CONFIG_460GT)
-#define RGMII_BASE		(CONFIG_SYS_PERIPHERAL_BASE + 0x1500)
-#elif defined(CONFIG_405EX)
-#define RGMII_BASE		(CONFIG_SYS_PERIPHERAL_BASE + 0xB00)
-#else
-#define RGMII_BASE		(CONFIG_SYS_PERIPHERAL_BASE + 0x0790)
-#endif
-#define RGMII_FER		(RGMII_BASE + 0x00)
-#define RGMII_SSR		(RGMII_BASE + 0x04)
-
-#if defined(CONFIG_460GT)
-#define RGMII1_BASE_OFFSET	0x100
-#endif
-
-/* RGMII Function Enable (FER) Register Bit Definitions */
-#define RGMII_FER_DIS		(0x00)
-#define RGMII_FER_RTBI		(0x04)
-#define RGMII_FER_RGMII		(0x05)
-#define RGMII_FER_TBI		(0x06)
-#define RGMII_FER_GMII		(0x07)
-#define RGMII_FER_MII		(RGMII_FER_GMII)
-
-#define RGMII_FER_V(__x)	((__x - 2) * 4)
-
-#define RGMII_FER_MDIO(__x)	(1 << (19 - (__x)))
-
-/* RGMII Speed Selection Register Bit Definitions */
-#define RGMII_SSR_SP_10MBPS	(0x00)
-#define RGMII_SSR_SP_100MBPS	(0x02)
-#define RGMII_SSR_SP_1000MBPS	(0x04)
-
-#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
-    defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
-    defined(CONFIG_405EX)
-#define RGMII_SSR_V(__x)	((__x) * 8)
-#else
-#define RGMII_SSR_V(__x)	((__x -2) * 8)
-#endif
-
-/*---------------------------------------------------------------------------+
-|  TCP/IP Acceleration Hardware (TAH) 440GX Only
-+---------------------------------------------------------------------------*/
-#if defined(CONFIG_440GX)
-#define TAH_BASE	(CONFIG_SYS_PERIPHERAL_BASE + 0x0B50)
-#define TAH_REVID	(TAH_BASE + 0x0)    /* Revision ID (RO)*/
-#define TAH_MR		(TAH_BASE + 0x10)   /* Mode Register (R/W) */
-#define TAH_SSR0	(TAH_BASE + 0x14)   /* Segment Size Reg 0 (R/W) */
-#define TAH_SSR1	(TAH_BASE + 0x18)   /* Segment Size Reg 1 (R/W) */
-#define TAH_SSR2	(TAH_BASE + 0x1C)   /* Segment Size Reg 2 (R/W) */
-#define TAH_SSR3	(TAH_BASE + 0x20)   /* Segment Size Reg 3 (R/W) */
-#define TAH_SSR4	(TAH_BASE + 0x24)   /* Segment Size Reg 4 (R/W) */
-#define TAH_SSR5	(TAH_BASE + 0x28)   /* Segment Size Reg 5 (R/W) */
-#define TAH_TSR		(TAH_BASE + 0x2C)   /* Transmit Status Register (RO) */
-
-/* TAH Revision */
-#define TAH_REV_RN_M		(0x000FFF00)	    /* Revision Number */
-#define TAH_REV_BN_M		(0x000000FF)	    /* Branch Revision Number */
-
-#define TAH_REV_RN_V		(8)
-#define TAH_REV_BN_V		(0)
-
-/* TAH Mode Register */
-#define TAH_MR_CVR	(0x80000000)	    /* Checksum verification on RX */
-#define TAH_MR_SR	(0x40000000)	    /* Software reset */
-#define TAH_MR_ST	(0x3F000000)	    /* Send Threshold */
-#define TAH_MR_TFS	(0x00E00000)	    /* Transmit FIFO size */
-#define TAH_MR_DTFP	(0x00100000)	    /* Disable TX FIFO parity */
-#define TAH_MR_DIG	(0x00080000)	    /* Disable interrupt generation */
-#define TAH_MR_RSVD	(0x0007FFFF)	    /* Reserved */
-
-#define TAH_MR_ST_V	(20)
-#define TAH_MR_TFS_V	(17)
-
-#define TAH_MR_TFS_2K	(0x1)	    /* Transmit FIFO size 2Kbyte */
-#define TAH_MR_TFS_4K	(0x2)	    /* Transmit FIFO size 4Kbyte */
-#define TAH_MR_TFS_6K	(0x3)	    /* Transmit FIFO size 6Kbyte */
-#define TAH_MR_TFS_8K	(0x4)	    /* Transmit FIFO size 8Kbyte */
-#define TAH_MR_TFS_10K	(0x5)	    /* Transmit FIFO size 10Kbyte (max)*/
-
-
-/* TAH Segment Size Registers 0:5 */
-#define TAH_SSR_RSVD0	(0xC0000000)	    /* Reserved */
-#define TAH_SSR_SS	(0x3FFE0000)	    /* Segment size in multiples of 2 */
-#define TAH_SSR_RSVD1	(0x0001FFFF)	    /* Reserved */
-
-/* TAH Transmit Status Register */
-#define TAH_TSR_TFTS	(0x80000000)	    /* Transmit FIFO too small */
-#define TAH_TSR_UH	(0x40000000)	    /* Unrecognized header */
-#define TAH_TSR_NIPF	(0x20000000)	    /* Not IPv4 */
-#define TAH_TSR_IPOP	(0x10000000)	    /* IP option present */
-#define TAH_TSR_NISF	(0x08000000)	    /* No IEEE SNAP format */
-#define TAH_TSR_ILTS	(0x04000000)	    /* IP length too short */
-#define TAH_TSR_IPFP	(0x02000000)	    /* IP fragment present */
-#define TAH_TSR_UP	(0x01000000)	    /* Unsupported protocol */
-#define TAH_TSR_TFP	(0x00800000)	    /* TCP flags present */
-#define TAH_TSR_SUDP	(0x00400000)	    /* Segmentation for UDP */
-#define TAH_TSR_DLM	(0x00200000)	    /* Data length mismatch */
-#define TAH_TSR_SIEEE	(0x00100000)	    /* Segmentation for IEEE */
-#define TAH_TSR_TFPE	(0x00080000)	    /* Transmit FIFO parity error */
-#define TAH_TSR_SSTS	(0x00040000)	    /* Segment size too small */
-#define TAH_TSR_RSVD	(0x0003FFFF)	    /* Reserved */
-#endif /* CONFIG_440GX */
-
-
-/* Ethernet MAC Regsiter Addresses */
-#if defined(CONFIG_440)
-#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
-    defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
-    defined(CONFIG_460EX) || defined(CONFIG_460GT)
-#define EMAC0_BASE		(CONFIG_SYS_PERIPHERAL_BASE + 0x0E00)
-#else
-#define EMAC0_BASE		(CONFIG_SYS_PERIPHERAL_BASE + 0x0800)
-#endif
-#else
-#if defined(CONFIG_405EZ) || defined(CONFIG_405EX)
-#define EMAC0_BASE		0xEF600900
-#else
-#define EMAC0_BASE		0xEF600800
-#endif
-#endif
-
-#if defined(CONFIG_440EPX)
-#define EMAC1_BASE		0xEF600F00
-#define EMAC1_MR1		(EMAC1_BASE + 0x04)
-#endif
-
-#define EMAC0_MR0		(EMAC0_BASE)
-#define EMAC0_MR1		(EMAC0_BASE + 0x04)
-#define EMAC0_TMR0		(EMAC0_BASE + 0x08)
-#define EMAC0_TMR1		(EMAC0_BASE + 0x0c)
-#define EMAC0_RXM		(EMAC0_BASE + 0x10)
-#define EMAC0_ISR		(EMAC0_BASE + 0x14)
-#define EMAC0_IER		(EMAC0_BASE + 0x18)
-#define EMAC0_IAH		(EMAC0_BASE + 0x1c)
-#define EMAC0_IAL		(EMAC0_BASE + 0x20)
-#define EMAC0_PTR		(EMAC0_BASE + 0x2c)
-#define EMAC0_PAUSE_TIME_REG	EMAC0_PTR
-#define EMAC0_IPGVR		(EMAC0_BASE + 0x58)
-#define EMAC0_I_FRAME_GAP_REG	EMAC0_IPGVR
-#define EMAC0_STACR		(EMAC0_BASE + 0x5c)
-#define EMAC0_TRTR		(EMAC0_BASE + 0x60)
-#define EMAC0_RWMR		(EMAC0_BASE + 0x64)
-#define EMAC0_RX_HI_LO_WMARK	EMAC0_RWMR
-
-/* bit definitions */
-/* MODE REG 0 */
-#define EMAC_MR0_RXI		(0x80000000)
-#define EMAC_MR0_TXI		(0x40000000)
-#define EMAC_MR0_SRST		(0x20000000)
-#define EMAC_MR0_TXE		(0x10000000)
-#define EMAC_MR0_RXE		(0x08000000)
-#define EMAC_MR0_WKE		(0x04000000)
-
-/* on 440GX EMAC_MR1 has a different layout! */
-#if defined(CONFIG_440GX) || \
-    defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
-    defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
-    defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
-    defined(CONFIG_405EX)
-/* MODE Reg 1 */
-#define EMAC_MR1_FDE		(0x80000000)
-#define EMAC_MR1_ILE		(0x40000000)
-#define EMAC_MR1_VLE		(0x20000000)
-#define EMAC_MR1_EIFC		(0x10000000)
-#define EMAC_MR1_APP		(0x08000000)
-#define EMAC_MR1_RSVD		(0x06000000)
-#define EMAC_MR1_IST		(0x01000000)
-#define EMAC_MR1_MF_1000GPCS	(0x00C00000)
-#define EMAC_MR1_MF_1000MBPS	(0x00800000)	/* 0's for 10MBPS */
-#define EMAC_MR1_MF_100MBPS	(0x00400000)
-#define EMAC_MR1_RFS_MASK	(0x00380000)
-#define EMAC_MR1_RFS_16K		(0x00280000)
-#define EMAC_MR1_RFS_8K		(0x00200000)
-#define EMAC_MR1_RFS_4K		(0x00180000)
-#define EMAC_MR1_RFS_2K		(0x00100000)
-#define EMAC_MR1_RFS_1K		(0x00080000)
-#define EMAC_MR1_TX_FIFO_MASK	(0x00070000)
-#define EMAC_MR1_TX_FIFO_16K	(0x00050000)
-#define EMAC_MR1_TX_FIFO_8K	(0x00040000)
-#define EMAC_MR1_TX_FIFO_4K	(0x00030000)
-#define EMAC_MR1_TX_FIFO_2K	(0x00020000)
-#define EMAC_MR1_TX_FIFO_1K	(0x00010000)
-#define EMAC_MR1_TR_MULTI	(0x00008000)	/* 0'x for single packet */
-#define EMAC_MR1_MWSW		(0x00007000)
-#define EMAC_MR1_JUMBO_ENABLE	(0x00000800)
-#define EMAC_MR1_IPPA		(0x000007c0)
-#define EMAC_MR1_IPPA_SET(id)	(((id) & 0x1f) << 6)
-#define EMAC_MR1_IPPA_GET(id)	(((id) >> 6) & 0x1f)
-#define EMAC_MR1_OBCI_GT100	(0x00000020)
-#define EMAC_MR1_OBCI_100	(0x00000018)
-#define EMAC_MR1_OBCI_83		(0x00000010)
-#define EMAC_MR1_OBCI_66		(0x00000008)
-#define EMAC_MR1_RSVD1		(0x00000007)
-#else /* defined(CONFIG_440GX) */
-/* EMAC_MR1 is the same on 405GP, 405GPr, 405EP, 440GP, 440EP */
-#define EMAC_MR1_FDE		0x80000000
-#define EMAC_MR1_ILE		0x40000000
-#define EMAC_MR1_VLE		0x20000000
-#define EMAC_MR1_EIFC		0x10000000
-#define EMAC_MR1_APP		0x08000000
-#define EMAC_MR1_AEMI		0x02000000
-#define EMAC_MR1_IST		0x01000000
-#define EMAC_MR1_MF_1000MBPS	0x00800000	/* 0's for 10MBPS */
-#define EMAC_MR1_MF_100MBPS	0x00400000
-#define EMAC_MR1_RFS_MASK	0x00300000
-#define EMAC_MR1_RFS_4K		0x00300000
-#define EMAC_MR1_RFS_2K		0x00200000
-#define EMAC_MR1_RFS_1K		0x00100000
-#define EMAC_MR1_RFS_512		0x00000000
-#define EMAC_MR1_TX_FIFO_MASK	0x000c0000
-#define EMAC_MR1_TX_FIFO_2K	0x00080000
-#define EMAC_MR1_TX_FIFO_1K	0x00040000
-#define EMAC_MR1_TX_FIFO_512	0x00000000
-#define EMAC_MR1_TR0_DEPEND	0x00010000	/* 0'x for single packet */
-#define EMAC_MR1_TR0_MULTI	0x00008000
-#define EMAC_MR1_TR1_DEPEND	0x00004000
-#define EMAC_MR1_TR1_MULTI	0x00002000
-#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
-#define EMAC_MR1_JUMBO_ENABLE	0x00001000
-#endif /* defined(CONFIG_440EP) || defined(CONFIG_440GR) */
-#endif /* defined(CONFIG_440GX) */
-
-#define EMAC_MR1_FIFO_MASK	(EMAC_MR1_RFS_MASK | EMAC_MR1_TX_FIFO_MASK)
-#if defined(CONFIG_405EZ)
-/* 405EZ only supports 512 bytes fifos */
-#define EMAC_MR1_FIFO_SIZE	(EMAC_MR1_RFS_512 | EMAC_MR1_TX_FIFO_512)
-#else
-/* Set receive fifo to 4k and tx fifo to 2k */
-#define EMAC_MR1_FIFO_SIZE	(EMAC_MR1_RFS_4K | EMAC_MR1_TX_FIFO_2K)
-#endif
-
-/* Transmit Mode Register 0 */
-#define EMAC_TMR0_GNP0		(0x80000000)
-#define EMAC_TMR0_GNP1		(0x40000000)
-#define EMAC_TMR0_GNPD		(0x20000000)
-#define EMAC_TMR0_FC		(0x10000000)
-
-/* Receive Mode Register */
-#define EMAC_RMR_SP		(0x80000000)
-#define EMAC_RMR_SFCS		(0x40000000)
-#define EMAC_RMR_ARRP		(0x20000000)
-#define EMAC_RMR_ARP		(0x10000000)
-#define EMAC_RMR_AROP		(0x08000000)
-#define EMAC_RMR_ARPI		(0x04000000)
-#define EMAC_RMR_PPP		(0x02000000)
-#define EMAC_RMR_PME		(0x01000000)
-#define EMAC_RMR_PMME		(0x00800000)
-#define EMAC_RMR_IAE		(0x00400000)
-#define EMAC_RMR_MIAE		(0x00200000)
-#define EMAC_RMR_BAE		(0x00100000)
-#define EMAC_RMR_MAE		(0x00080000)
-
-/* Interrupt Status & enable Regs */
-#define EMAC_ISR_OVR		(0x02000000)
-#define EMAC_ISR_PP		(0x01000000)
-#define EMAC_ISR_BP		(0x00800000)
-#define EMAC_ISR_RP		(0x00400000)
-#define EMAC_ISR_SE		(0x00200000)
-#define EMAC_ISR_SYE		(0x00100000)
-#define EMAC_ISR_BFCS		(0x00080000)
-#define EMAC_ISR_PTLE		(0x00040000)
-#define EMAC_ISR_ORE		(0x00020000)
-#define EMAC_ISR_IRE		(0x00010000)
-#define EMAC_ISR_DBDM		(0x00000200)
-#define EMAC_ISR_DB0		(0x00000100)
-#define EMAC_ISR_SE0		(0x00000080)
-#define EMAC_ISR_TE0		(0x00000040)
-#define EMAC_ISR_DB1		(0x00000020)
-#define EMAC_ISR_SE1		(0x00000010)
-#define EMAC_ISR_TE1		(0x00000008)
-#define EMAC_ISR_MOS		(0x00000002)
-#define EMAC_ISR_MOF		(0x00000001)
-
-/* STA CONTROL REG */
-#define EMAC_STACR_OC		(0x00008000)
-#define EMAC_STACR_PHYE		(0x00004000)
-
-#ifdef CONFIG_IBM_EMAC4_V4	/* EMAC4 V4 changed bit setting */
-#define EMAC_STACR_INDIRECT_MODE (0x00002000)
-#define EMAC_STACR_WRITE	(0x00000800) /* $BUC */
-#define EMAC_STACR_READ		(0x00001000) /* $BUC */
-#define EMAC_STACR_OP_MASK	(0x00001800)
-#define EMAC_STACR_MDIO_ADDR	(0x00000000)
-#define EMAC_STACR_MDIO_WRITE	(0x00000800)
-#define EMAC_STACR_MDIO_READ	(0x00001800)
-#define EMAC_STACR_MDIO_READ_INC (0x00001000)
-#else
-#define EMAC_STACR_WRITE	(0x00002000)
-#define EMAC_STACR_READ		(0x00001000)
-#endif
-
-#define EMAC_STACR_CLK_83MHZ	(0x00000800)  /* 0's for 50Mhz */
-#define EMAC_STACR_CLK_66MHZ	(0x00000400)
-#define EMAC_STACR_CLK_100MHZ	(0x00000C00)
-
-/* Transmit Request Threshold Register */
-#define EMAC_TRTR_256		(0x18000000)   /* 0's for 64 Bytes */
-#define EMAC_TRTR_192		(0x10000000)
-#define EMAC_TRTR_128		(0x01000000)
-
-/* the follwing defines are for the MadMAL status and control registers. */
-/* For bits 0..5 look at the mal.h file					 */
-#define EMAC_TX_CTRL_GFCS	(0x0200)
-#define EMAC_TX_CTRL_GP		(0x0100)
-#define EMAC_TX_CTRL_ISA	(0x0080)
-#define EMAC_TX_CTRL_RSA	(0x0040)
-#define EMAC_TX_CTRL_IVT	(0x0020)
-#define EMAC_TX_CTRL_RVT	(0x0010)
-
-#define EMAC_TX_CTRL_DEFAULT (EMAC_TX_CTRL_GFCS |EMAC_TX_CTRL_GP)
-
-#define EMAC_TX_ST_BFCS		(0x0200)
-#define EMAC_TX_ST_BPP		(0x0100)
-#define EMAC_TX_ST_LCS		(0x0080)
-#define EMAC_TX_ST_ED		(0x0040)
-#define EMAC_TX_ST_EC		(0x0020)
-#define EMAC_TX_ST_LC		(0x0010)
-#define EMAC_TX_ST_MC		(0x0008)
-#define EMAC_TX_ST_SC		(0x0004)
-#define EMAC_TX_ST_UR		(0x0002)
-#define EMAC_TX_ST_SQE		(0x0001)
-
-#define EMAC_TX_ST_DEFAULT	(0x03F3)
-
-
-/* madmal receive status / Control bits */
-
-#define EMAC_RX_ST_OE		(0x0200)
-#define EMAC_RX_ST_PP		(0x0100)
-#define EMAC_RX_ST_BP		(0x0080)
-#define EMAC_RX_ST_RP		(0x0040)
-#define EMAC_RX_ST_SE		(0x0020)
-#define EMAC_RX_ST_AE		(0x0010)
-#define EMAC_RX_ST_BFCS		(0x0008)
-#define EMAC_RX_ST_PTL		(0x0004)
-#define EMAC_RX_ST_ORE		(0x0002)
-#define EMAC_RX_ST_IRE		(0x0001)
-/* all the errors we care about */
-#define EMAC_RX_ERRORS		(0x03FF)
-
-#endif /* _PPC4XX_ENET_H_ */
diff --git a/arch/powerpc/include/asm/ppc4xx-gpio.h b/arch/powerpc/include/asm/ppc4xx-gpio.h
deleted file mode 100644
index 90a62ea..0000000
--- a/arch/powerpc/include/asm/ppc4xx-gpio.h
+++ /dev/null
@@ -1,103 +0,0 @@
-/*
- * (C) Copyright 2007-2008
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef __ASM_PPC_GPIO_H
-#define __ASM_PPC_GPIO_H
-
-#include <asm/types.h>
-
-/* 4xx PPC's have 2 GPIO controllers */
-#if defined(CONFIG_405EZ) ||					\
-	defined(CONFIG_440EP) || defined(CONFIG_440GR) ||	\
-	defined(CONFIG_440EPX) || defined(CONFIG_440GRX) ||	\
-	defined(CONFIG_460EX) || defined(CONFIG_460GT)
-#define GPIO_GROUP_MAX	2
-#else
-#define GPIO_GROUP_MAX	1
-#endif
-
-/* GPIO controller */
-struct ppc4xx_gpio {
-	u32 or;		/* Output Control */
-	u32 tcr;	/* Tri-State Control */
-	u32 osl;	/* Output Select 16..31 */
-	u32 osh;	/* Output Select 0..15 */
-	u32 tsl;	/* Tri-State Select 16..31 */
-	u32 tsh;	/* Tri-State Select 0..15 */
-	u32 odr;	/* Open Drain */
-	u32 ir;		/* Input */
-	u32 rr1;	/* Receive Register 1 */
-	u32 rr2;	/* Receive Register 2 */
-	u32 rr3;	/* Receive Register 3 */
-	u32 reserved;
-	u32 is1l;	/* Input Select 1 16..31 */
-	u32 is1h;	/* Input Select 1 0..15 */
-	u32 is2l;	/* Input Select 2 16..31 */
-	u32 is2h;	/* Input Select 2 0..15 */
-	u32 is3l;	/* Input Select 3 16..31 */
-	u32 is3h;	/* Input Select 3 0..15 */
-};
-
-/* Offsets */
-#define GPIOx_OR	0x00		/* GPIO Output Register */
-#define GPIOx_TCR	0x04		/* GPIO Three-State Control Register */
-#define GPIOx_OSL	0x08		/* GPIO Output Select Register (Bits 0-31) */
-#define GPIOx_OSH	0x0C		/* GPIO Ouput Select Register (Bits 32-63) */
-#define GPIOx_TSL	0x10		/* GPIO Three-State Select Register (Bits 0-31) */
-#define GPIOx_TSH	0x14		/* GPIO Three-State Select Register  (Bits 32-63) */
-#define GPIOx_ODR	0x18		/* GPIO Open drain Register */
-#define GPIOx_IR	0x1C		/* GPIO Input Register */
-#define GPIOx_RR1	0x20		/* GPIO Receive Register 1 */
-#define GPIOx_RR2	0x24		/* GPIO Receive Register 2 */
-#define GPIOx_RR3	0x28		/* GPIO Receive Register 3 */
-#define GPIOx_IS1L	0x30		/* GPIO Input Select Register 1 (Bits 0-31) */
-#define GPIOx_IS1H	0x34		/* GPIO Input Select Register 1 (Bits 32-63) */
-#define GPIOx_IS2L	0x38		/* GPIO Input Select Register 2 (Bits 0-31) */
-#define GPIOx_IS2H	0x3C		/* GPIO Input Select Register 2 (Bits 32-63) */
-#define GPIOx_IS3L	0x40		/* GPIO Input Select Register 3 (Bits 0-31) */
-#define GPIOx_IS3H	0x44		/* GPIO Input Select Register 3 (Bits 32-63) */
-
-#define GPIO_OR(x)	(x+GPIOx_OR)	/* GPIO Output Register */
-#define GPIO_TCR(x)	(x+GPIOx_TCR)	/* GPIO Three-State Control Register */
-#define GPIO_OS(x)	(x+GPIOx_OSL)	/* GPIO Output Select Register High or Low */
-#define GPIO_TS(x)	(x+GPIOx_TSL)	/* GPIO Three-state Control Reg High or Low */
-#define GPIO_IS1(x)	(x+GPIOx_IS1L)	/* GPIO Input register1 High or Low */
-#define GPIO_IS2(x)	(x+GPIOx_IS2L)	/* GPIO Input register2 High or Low */
-#define GPIO_IS3(x)	(x+GPIOx_IS3L)	/* GPIO Input register3 High or Low */
-
-#define GPIO0		0
-#define GPIO1		1
-
-#define GPIO_MAX	32
-#define GPIO_ALT1_SEL	0x40000000
-#define GPIO_ALT2_SEL	0x80000000
-#define GPIO_ALT3_SEL	0xc0000000
-#define GPIO_IN_SEL	0x40000000
-#define GPIO_MASK	0xc0000000
-
-#define GPIO_VAL(gpio)	(0x80000000 >> (gpio))
-
-#ifndef __ASSEMBLY__
-typedef enum gpio_select { GPIO_SEL, GPIO_ALT1, GPIO_ALT2, GPIO_ALT3 } gpio_select_t;
-typedef enum gpio_driver { GPIO_DIS, GPIO_IN, GPIO_OUT, GPIO_BI } gpio_driver_t;
-typedef enum gpio_out	 { GPIO_OUT_0, GPIO_OUT_1, GPIO_OUT_NO_CHG } gpio_out_t;
-
-typedef struct {
-	unsigned long	add;	/* gpio core base address	*/
-	gpio_driver_t	in_out;	/* Driver Setting		*/
-	gpio_select_t	alt_nb;	/* Selected Alternate		*/
-	gpio_out_t	out_val;/* Default Output Value		*/
-} gpio_param_s;
-#endif
-
-void gpio_config(int pin, int in_out, int gpio_alt, int out_val);
-void gpio_write_bit(int pin, int val);
-int gpio_read_out_bit(int pin);
-int gpio_read_in_bit(int pin);
-void gpio_set_chip_configuration(void);
-
-#endif /* __ASM_PPC_GPIO_H */
diff --git a/arch/powerpc/include/asm/ppc4xx-i2c.h b/arch/powerpc/include/asm/ppc4xx-i2c.h
deleted file mode 100644
index df97f17..0000000
--- a/arch/powerpc/include/asm/ppc4xx-i2c.h
+++ /dev/null
@@ -1,95 +0,0 @@
-/*
- * (C) Copyright 2007-2009
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef _4xx_i2c_h_
-#define _4xx_i2c_h_
-
-#define IIC_OK		0
-#define IIC_NOK		1
-#define IIC_NOK_LA	2		/* Lost arbitration */
-#define IIC_NOK_ICT	3		/* Incomplete transfer */
-#define IIC_NOK_XFRA	4		/* Transfer aborted */
-#define IIC_NOK_DATA	5		/* No data in buffer */
-#define IIC_NOK_TOUT	6		/* Transfer timeout */
-
-#define IIC_TIMEOUT	1		/* 1 second */
-
-struct ppc4xx_i2c {
-	u8 mdbuf;
-	u8 res1;
-	u8 sdbuf;
-	u8 res2;
-	u8 lmadr;
-	u8 hmadr;
-	u8 cntl;
-	u8 mdcntl;
-	u8 sts;
-	u8 extsts;
-	u8 lsadr;
-	u8 hsadr;
-	u8 clkdiv;
-	u8 intrmsk;
-	u8 xfrcnt;
-	u8 xtcntlss;
-	u8 directcntl;
-	u8 intr;
-};
-
-/* MDCNTL Register Bit definition */
-#define IIC_MDCNTL_HSCL		0x01
-#define IIC_MDCNTL_EUBS		0x02
-#define IIC_MDCNTL_EINT		0x04
-#define IIC_MDCNTL_ESM		0x08
-#define IIC_MDCNTL_FSM		0x10
-#define IIC_MDCNTL_EGC		0x20
-#define IIC_MDCNTL_FMDB		0x40
-#define IIC_MDCNTL_FSDB		0x80
-
-/* CNTL Register Bit definition */
-#define IIC_CNTL_PT		0x01
-#define IIC_CNTL_READ		0x02
-#define IIC_CNTL_CHT		0x04
-#define IIC_CNTL_RPST		0x08
-/* bit 2/3 for Transfer count*/
-#define IIC_CNTL_AMD		0x40
-#define IIC_CNTL_HMT		0x80
-
-/* STS Register Bit definition */
-#define IIC_STS_PT		0x01
-#define IIC_STS_IRQA		0x02
-#define IIC_STS_ERR		0x04
-#define IIC_STS_SCMP		0x08
-#define IIC_STS_MDBF		0x10
-#define IIC_STS_MDBS		0x20
-#define IIC_STS_SLPR		0x40
-#define IIC_STS_SSS		0x80
-
-/* EXTSTS Register Bit definition */
-#define IIC_EXTSTS_XFRA		0x01
-#define IIC_EXTSTS_ICT		0x02
-#define IIC_EXTSTS_LA		0x04
-#define IIC_EXTSTS_BCS_MASK	0x70
-#define IIC_EXTSTS_BCS_FREE	0x40
-
-/* XTCNTLSS Register Bit definition */
-#define IIC_XTCNTLSS_SRST	0x01
-#define IIC_XTCNTLSS_EPI	0x02
-#define IIC_XTCNTLSS_SDBF	0x04
-#define IIC_XTCNTLSS_SBDD	0x08
-#define IIC_XTCNTLSS_SWS	0x10
-#define IIC_XTCNTLSS_SWC	0x20
-#define IIC_XTCNTLSS_SRS	0x40
-#define IIC_XTCNTLSS_SRC	0x80
-
-/* IICx_DIRECTCNTL register */
-#define IIC_DIRCNTL_SDAC	0x08
-#define IIC_DIRCNTL_SCC		0x04
-#define IIC_DIRCNTL_MSDA	0x02
-#define IIC_DIRCNTL_MSC		0x01
-
-#define DIRCTNL_FREE(v)		(((v) & 0x0f) == 0x0f)
-#endif
diff --git a/arch/powerpc/include/asm/ppc4xx-isram.h b/arch/powerpc/include/asm/ppc4xx-isram.h
deleted file mode 100644
index 2ae399f..0000000
--- a/arch/powerpc/include/asm/ppc4xx-isram.h
+++ /dev/null
@@ -1,62 +0,0 @@
-/*
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef _PPC4xx_ISRAM_H_
-#define _PPC4xx_ISRAM_H_
-
-/*
- * Internal SRAM
- */
-#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
-#define ISRAM0_DCR_BASE 0x380
-#else
-#define ISRAM0_DCR_BASE 0x020
-#endif
-#define ISRAM0_SB0CR	(ISRAM0_DCR_BASE+0x00)	/* SRAM bank config 0*/
-#define ISRAM0_SB1CR	(ISRAM0_DCR_BASE+0x01)	/* SRAM bank config 1*/
-#define ISRAM0_SB2CR	(ISRAM0_DCR_BASE+0x02)	/* SRAM bank config 2*/
-#define ISRAM0_SB3CR	(ISRAM0_DCR_BASE+0x03)	/* SRAM bank config 3*/
-#define ISRAM0_BEAR	(ISRAM0_DCR_BASE+0x04)	/* SRAM bus error addr reg */
-#define ISRAM0_BESR0	(ISRAM0_DCR_BASE+0x05)	/* SRAM bus error status reg 0 */
-#define ISRAM0_BESR1	(ISRAM0_DCR_BASE+0x06)	/* SRAM bus error status reg 1 */
-#define ISRAM0_PMEG	(ISRAM0_DCR_BASE+0x07)	/* SRAM power management */
-#define ISRAM0_CID	(ISRAM0_DCR_BASE+0x08)	/* SRAM bus core id reg */
-#define ISRAM0_REVID	(ISRAM0_DCR_BASE+0x09)	/* SRAM bus revision id reg */
-#define ISRAM0_DPC	(ISRAM0_DCR_BASE+0x0a)	/* SRAM data parity check reg */
-
-#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
-#define ISRAM1_DCR_BASE 0x0B0
-#define ISRAM1_SB0CR	(ISRAM1_DCR_BASE+0x00)	/* SRAM1 bank config 0*/
-#define ISRAM1_BEAR	(ISRAM1_DCR_BASE+0x04)	/* SRAM1 bus error addr reg */
-#define ISRAM1_BESR0	(ISRAM1_DCR_BASE+0x05)	/* SRAM1 bus error status reg 0 */
-#define ISRAM1_BESR1	(ISRAM1_DCR_BASE+0x06)	/* SRAM1 bus error status reg 1 */
-#define ISRAM1_PMEG	(ISRAM1_DCR_BASE+0x07)	/* SRAM1 power management */
-#define ISRAM1_CID	(ISRAM1_DCR_BASE+0x08)	/* SRAM1 bus core id reg */
-#define ISRAM1_REVID	(ISRAM1_DCR_BASE+0x09)	/* SRAM1 bus revision id reg */
-#define ISRAM1_DPC	(ISRAM1_DCR_BASE+0x0a)	/* SRAM1 data parity check reg */
-#endif /* CONFIG_460EX || CONFIG_460GT */
-
-#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
-#define ISRAM1_SIZE 0x0984 /* OCM size 64k */
-#endif
-
-/*
- * L2 Cache
- */
-#if defined (CONFIG_440GX) || \
-    defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
-    defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
-    defined(CONFIG_460SX)
-#define L2_CACHE_BASE	0x030
-#define L2_CACHE_CFG	(L2_CACHE_BASE+0x00)	/* L2 Cache Config      */
-#define L2_CACHE_CMD	(L2_CACHE_BASE+0x01)	/* L2 Cache Command     */
-#define L2_CACHE_ADDR	(L2_CACHE_BASE+0x02)	/* L2 Cache Address     */
-#define L2_CACHE_DATA	(L2_CACHE_BASE+0x03)	/* L2 Cache Data        */
-#define L2_CACHE_STAT	(L2_CACHE_BASE+0x04)	/* L2 Cache Status      */
-#define L2_CACHE_CVER	(L2_CACHE_BASE+0x05)	/* L2 Cache Revision ID */
-#define L2_CACHE_SNP0	(L2_CACHE_BASE+0x06)	/* L2 Cache Snoop reg 0 */
-#define L2_CACHE_SNP1	(L2_CACHE_BASE+0x07)	/* L2 Cache Snoop reg 1 */
-#endif /* CONFIG_440GX */
-
-#endif /* _PPC4xx_ISRAM_H_ */
diff --git a/arch/powerpc/include/asm/ppc4xx-mal.h b/arch/powerpc/include/asm/ppc4xx-mal.h
deleted file mode 100644
index ef8b174..0000000
--- a/arch/powerpc/include/asm/ppc4xx-mal.h
+++ /dev/null
@@ -1,149 +0,0 @@
-/* include/mal.h, openbios_walnut, walnut_bios 8/6/99 08:48:40 */
-/*
- * SPDX-License-Identifier:	GPL-2.0	IBM-pibs
- */
-/*----------------------------------------------------------------------------+
-|
-|  File Name:	mal.h
-|
-|  Function:	Header file for the MAL (MADMAL) macro on the 405GP.
-|
-|  Author:	Mark Wisner
-|
-|  Change Activity-
-|
-|  Date	       Description of Change					   BY
-|  ---------   ---------------------					   ---
-|  29-Apr-99   Created							   MKW
-|
-+----------------------------------------------------------------------------*/
-/*----------------------------------------------------------------------------+
-|  17-Nov-03  Travis B. Sawyer, Sandburst Corporation, tsawyer@sandburst.com
-|	      Added register bit definitions to support multiple channels
-+----------------------------------------------------------------------------*/
-#ifndef _mal_h_
-#define _mal_h_
-
-#if !defined(MAL_DCR_BASE)
-#define MAL_DCR_BASE	0x180
-#endif
-#define MAL0_CFG	(MAL_DCR_BASE + 0x00)	/* MAL Config reg	*/
-#define MAL0_ESR	(MAL_DCR_BASE + 0x01)	/* Error Status (Read/Clear) */
-#define MAL0_IER	(MAL_DCR_BASE + 0x02)	/* Interrupt enable */
-#define MAL0_TXCASR	(MAL_DCR_BASE + 0x04)	/* TX Channel active (set) */
-#define MAL0_TXCARR	(MAL_DCR_BASE + 0x05)	/* TX Channel active (reset) */
-#define MAL0_TXEOBISR	(MAL_DCR_BASE + 0x06)	/* TX End of buffer int status*/
-#define MAL0_TXDEIR	(MAL_DCR_BASE + 0x07)	/* TX Descr. Error Int */
-#define MAL0_TXBADDR	(MAL_DCR_BASE + 0x09)	/* TX descriptor base addr*/
-#define MAL0_RXCASR	(MAL_DCR_BASE + 0x10)	/* RX Channel active (set) */
-#define MAL0_RXCARR	(MAL_DCR_BASE + 0x11)	/* RX Channel active (reset) */
-#define MAL0_RXEOBISR	(MAL_DCR_BASE + 0x12)	/* RX End of buffer int status*/
-#define MAL0_RXDEIR	(MAL_DCR_BASE + 0x13)	/* RX Descr. Error Int */
-#define MAL0_RXBADDR	(MAL_DCR_BASE + 0x15)	/* RX descriptor base addr */
-#define MAL0_TXCTP0R	(MAL_DCR_BASE + 0x20)	/* TX 0 Channel table pointer */
-#define MAL0_TXCTP1R	(MAL_DCR_BASE + 0x21)	/* TX 1 Channel table pointer */
-#define MAL0_TXCTP2R	(MAL_DCR_BASE + 0x22)	/* TX 2 Channel table pointer */
-#define MAL0_TXCTP3R	(MAL_DCR_BASE + 0x23)	/* TX 3 Channel table pointer */
-#define MAL0_RXCTP0R	(MAL_DCR_BASE + 0x40)	/* RX 0 Channel table pointer */
-#define MAL0_RXCTP1R	(MAL_DCR_BASE + 0x41)	/* RX 1 Channel table pointer */
-#define MAL0_RCBS0	(MAL_DCR_BASE + 0x60)	/* RX 0 Channel buffer size */
-#define MAL0_RCBS1	(MAL_DCR_BASE + 0x61)	/* RX 1 Channel buffer size */
-#if defined(CONFIG_440GX) || \
-    defined(CONFIG_460EX) || defined(CONFIG_460GT)
-#define MAL0_RXCTP2R	(MAL_DCR_BASE + 0x42)	/* RX 2 Channel table pointer */
-#define MAL0_RXCTP3R	(MAL_DCR_BASE + 0x43)	/* RX 3 Channel table pointer */
-#define MAL0_RXCTP8R	(MAL_DCR_BASE + 0x48)	/* RX 8 Channel table pointer */
-#define MAL0_RXCTP16R	(MAL_DCR_BASE + 0x50)	/* RX 16 Channel table pointer*/
-#define MAL0_RXCTP24R	(MAL_DCR_BASE + 0x58)	/* RX 24 Channel table pointer*/
-#define MAL0_RCBS2	(MAL_DCR_BASE + 0x62)	/* RX 2 Channel buffer size */
-#define MAL0_RCBS3	(MAL_DCR_BASE + 0x63)	/* RX 3 Channel buffer size */
-#define MAL0_RCBS8	(MAL_DCR_BASE + 0x68)	/* RX 8 Channel buffer size */
-#define MAL0_RCBS16	(MAL_DCR_BASE + 0x70)	/* RX 16 Channel buffer size */
-#define MAL0_RCBS24	(MAL_DCR_BASE + 0x78)	/* RX 24 Channel buffer size */
-#endif /* CONFIG_440GX */
-
-/* MADMAL transmit and receive status/control bits  */
-/* for COMMAC bits, refer to the COMMAC header file */
-
-#define MAL_TX_CTRL_READY 0x8000
-#define MAL_TX_CTRL_WRAP  0x4000
-#define MAL_TX_CTRL_CM	  0x2000
-#define MAL_TX_CTRL_LAST  0x1000
-#define MAL_TX_CTRL_INTR  0x0400
-
-#define MAL_RX_CTRL_EMPTY 0x8000
-#define MAL_RX_CTRL_WRAP  0x4000
-#define MAL_RX_CTRL_CM	  0x2000
-#define MAL_RX_CTRL_LAST  0x1000
-#define MAL_RX_CTRL_FIRST 0x0800
-#define MAL_RX_CTRL_INTR  0x0400
-
-      /* Configuration Reg  */
-#define MAL_CR_MMSR	  0x80000000
-#define MAL_CR_PLBP_1	  0x00400000   /* lowsest is 00 */
-#define MAL_CR_PLBP_2	  0x00800000
-#define MAL_CR_PLBP_3	  0x00C00000   /* highest	*/
-#define MAL_CR_GA	  0x00200000
-#define MAL_CR_OA	  0x00100000
-#define MAL_CR_PLBLE	  0x00080000
-#define MAL_CR_PLBLT_1	0x00040000
-#define MAL_CR_PLBLT_2	0x00020000
-#define MAL_CR_PLBLT_3	0x00010000
-#define MAL_CR_PLBLT_4	0x00008000
-#define MAL_CR_PLBLT_DEFAULT 0x00078000 /* ????? */
-#define MAL_CR_PLBB	  0x00004000
-#define MAL_CR_OPBBL	  0x00000080
-#define MAL_CR_EOPIE	  0x00000004
-#define MAL_CR_LEA	  0x00000002
-#define MAL_CR_MSD	  0x00000001
-
-    /* Error Status Reg	   */
-#define MAL_ESR_EVB	  0x80000000
-#define MAL_ESR_CID	  0x40000000
-#define MAL_ESR_DE	  0x00100000
-#define MAL_ESR_ONE	  0x00080000
-#define MAL_ESR_OTE	  0x00040000
-#define MAL_ESR_OSE	  0x00020000
-#define MAL_ESR_PEIN	  0x00010000
-      /* same bit position as the IER */
-      /* VV			 VV   */
-#define MAL_ESR_DEI	  0x00000010
-#define MAL_ESR_ONEI	  0x00000008
-#define MAL_ESR_OTEI	  0x00000004
-#define MAL_ESR_OSEI	  0x00000002
-#define MAL_ESR_PBEI	  0x00000001
-      /* ^^			 ^^   */
-      /* Mal IER		      */
-#if defined(CONFIG_440SPE) || \
-    defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
-    defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
-    defined(CONFIG_405EX)
-#define MAL_IER_PT	  0x00000080
-#define MAL_IER_PRE	  0x00000040
-#define MAL_IER_PWE	  0x00000020
-#define MAL_IER_DE	  0x00000010
-#define MAL_IER_OTE	  0x00000004
-#define MAL_IER_OE	  0x00000002
-#define MAL_IER_PE	  0x00000001
-#else
-#define MAL_IER_DE	  0x00000010
-#define MAL_IER_NE	  0x00000008
-#define MAL_IER_TE	  0x00000004
-#define MAL_IER_OPBE	  0x00000002
-#define MAL_IER_PLBE	  0x00000001
-#endif
-
-/* MAL Channel Active Set and Reset Registers */
-#define MAL_TXRX_CASR	(0x80000000)
-
-#define MAL_TXRX_CASR_V(__x)  (__x)  /* Channel 0 shifts 0, channel 1 shifts 1, etc */
-
-
-/* MAL Buffer Descriptor structure */
-typedef struct {
-  short	 ctrl;		    /* MAL / Commac status control bits */
-  short	 data_len;	    /* Max length is 4K-1 (12 bits)	*/
-  char	*data_ptr;	    /* pointer to actual data buffer	*/
-} mal_desc_t;
-
-#endif
diff --git a/arch/powerpc/include/asm/ppc4xx-sdram.h b/arch/powerpc/include/asm/ppc4xx-sdram.h
deleted file mode 100644
index e6fed83..0000000
--- a/arch/powerpc/include/asm/ppc4xx-sdram.h
+++ /dev/null
@@ -1,1402 +0,0 @@
-/*
- * (C) Copyright 2008
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef _PPC4xx_SDRAM_H_
-#define _PPC4xx_SDRAM_H_
-
-#if defined(CONFIG_SDRAM_PPC4xx_IBM_SDRAM)
-
-/*
- * SDRAM Controller
- */
-
-#ifndef CONFIG_405EP
-#define SDRAM0_BESR0	0x00	/* bus error syndrome reg a		*/
-#define SDRAM0_BESRS0	0x04	/* bus error syndrome reg set a		*/
-#define SDRAM0_BESR1	0x08	/* bus error syndrome reg b		*/
-#define SDRAM0_BESRS1	0x0c	/* bus error syndrome reg set b		*/
-#define SDRAM0_BEAR	0x10	/* bus error address reg		*/
-#endif
-#define SDRAM0_CFG	0x20	/* memory controller options 1		*/
-#define SDRAM0_STATUS	0x24	/* memory status			*/
-#define SDRAM0_RTR	0x30	/* refresh timer reg			*/
-#define SDRAM0_PMIT	0x34	/* power management idle timer		*/
-#define SDRAM0_B0CR	0x40	/* memory bank 0 configuration		*/
-#define SDRAM0_B1CR	0x44	/* memory bank 1 configuration		*/
-#ifndef CONFIG_405EP
-#define SDRAM0_B2CR	0x48	/* memory bank 2 configuration		*/
-#define SDRAM0_B3CR	0x4c	/* memory bank 3 configuration		*/
-#endif
-#define SDRAM0_TR	0x80	/* timing reg 1				*/
-#ifndef CONFIG_405EP
-#define SDRAM0_ECCCFG	0x94	/* ECC configuration			*/
-#define SDRAM0_ECCESR	0x98	/* ECC error status			*/
-#endif
-
-#endif /* CONFIG_SDRAM_PPC4xx_IBM_SDRAM */
-
-#if defined(CONFIG_SDRAM_PPC4xx_IBM_DDR)
-
-/*
- * Memory controller registers
- */
-#define SDRAM_CFG0	0x20	/* memory controller options 0		*/
-#define SDRAM_CFG1	0x21	/* memory controller options 1		*/
-
-#define SDRAM0_BESR0	0x0000	/* bus error status reg 0		*/
-#define SDRAM0_BESR1	0x0008	/* bus error status reg 1		*/
-#define SDRAM0_BEAR	0x0010	/* bus error address reg		*/
-#define SDRAM0_SLIO	0x0018	/* ddr sdram slave interface options	*/
-#define SDRAM0_CFG0	0x0020	/* ddr sdram options 0			*/
-#define SDRAM0_CFG1	0x0021	/* ddr sdram options 1			*/
-#define SDRAM0_DEVOPT	0x0022	/* ddr sdram device options		*/
-#define SDRAM0_MCSTS	0x0024	/* memory controller status		*/
-#define SDRAM0_RTR	0x0030	/* refresh timer register		*/
-#define SDRAM0_PMIT	0x0034	/* power management idle timer		*/
-#define SDRAM0_UABBA	0x0038	/* plb UABus base address		*/
-#define SDRAM0_B0CR	0x0040	/* ddr sdram bank 0 configuration	*/
-#define SDRAM0_B1CR	0x0044	/* ddr sdram bank 1 configuration	*/
-#define SDRAM0_B2CR	0x0048	/* ddr sdram bank 2 configuration	*/
-#define SDRAM0_B3CR	0x004c	/* ddr sdram bank 3 configuration	*/
-#define SDRAM0_TR0	0x0080	/* sdram timing register 0		*/
-#define SDRAM0_TR1	0x0081	/* sdram timing register 1		*/
-#define SDRAM0_CLKTR	0x0082	/* ddr clock timing register		*/
-#define SDRAM0_WDDCTR	0x0083	/* write data/dm/dqs clock timing reg	*/
-#define SDRAM0_DLYCAL	0x0084	/* delay line calibration register	*/
-#define SDRAM0_ECCESR	0x0098	/* ECC error status			*/
-
-/*
- * Memory Controller Options 0
- */
-#define SDRAM_CFG0_DCEN		0x80000000	/* SDRAM Controller Enable	*/
-#define SDRAM_CFG0_MCHK_MASK	0x30000000	/* Memory data errchecking mask */
-#define SDRAM_CFG0_MCHK_NON	0x00000000	/* No ECC generation		*/
-#define SDRAM_CFG0_MCHK_GEN	0x20000000	/* ECC generation		*/
-#define SDRAM_CFG0_MCHK_CHK	0x30000000	/* ECC generation and checking	*/
-#define SDRAM_CFG0_RDEN		0x08000000	/* Registered DIMM enable	*/
-#define SDRAM_CFG0_PMUD		0x04000000	/* Page management unit		*/
-#define SDRAM_CFG0_DMWD_MASK	0x02000000	/* DRAM width mask		*/
-#define SDRAM_CFG0_DMWD_32	0x00000000	/* 32 bits			*/
-#define SDRAM_CFG0_DMWD_64	0x02000000	/* 64 bits			*/
-#define SDRAM_CFG0_UIOS_MASK	0x00C00000	/* Unused IO State		*/
-#define SDRAM_CFG0_PDP		0x00200000	/* Page deallocation policy	*/
-
-/*
- * Memory Controller Options 1
- */
-#define SDRAM_CFG1_SRE		0x80000000	/* Self-Refresh Entry		*/
-#define SDRAM_CFG1_PMEN		0x40000000	/* Power Management Enable	*/
-
-/*
- * SDRAM DEVPOT Options
- */
-#define SDRAM_DEVOPT_DLL	0x80000000
-#define SDRAM_DEVOPT_DS		0x40000000
-
-/*
- * SDRAM MCSTS Options
- */
-#define SDRAM_MCSTS_MRSC	0x80000000
-#define SDRAM_MCSTS_SRMS	0x40000000
-#define SDRAM_MCSTS_CIS		0x20000000
-#define SDRAM_MCSTS_IDLE_NOT	0x00000000	/* Mem contr not idle		*/
-
-/*
- * SDRAM Refresh Timer Register
- */
-#define SDRAM_RTR_RINT_MASK	  0xFFFF0000
-#define SDRAM_RTR_RINT_ENCODE(n)  (((n) << 16) & SDRAM_RTR_RINT_MASK)
-
-/*
- * SDRAM UABus Base Address Reg
- */
-#define SDRAM_UABBA_UBBA_MASK	0x0000000F
-
-/*
- * Memory Bank 0-7 configuration
- */
-#define SDRAM_BXCR_SDBA_MASK	0xff800000	  /* Base address	      */
-#define SDRAM_BXCR_SDSZ_MASK	0x000e0000	  /* Size		      */
-#define SDRAM_BXCR_SDSZ_8	0x00020000	  /*   8M		      */
-#define SDRAM_BXCR_SDSZ_16	0x00040000	  /*  16M		      */
-#define SDRAM_BXCR_SDSZ_32	0x00060000	  /*  32M		      */
-#define SDRAM_BXCR_SDSZ_64	0x00080000	  /*  64M		      */
-#define SDRAM_BXCR_SDSZ_128	0x000a0000	  /* 128M		      */
-#define SDRAM_BXCR_SDSZ_256	0x000c0000	  /* 256M		      */
-#define SDRAM_BXCR_SDSZ_512	0x000e0000	  /* 512M		      */
-#define SDRAM_BXCR_SDAM_MASK	0x0000e000	  /* Addressing mode	      */
-#define SDRAM_BXCR_SDAM_1	0x00000000	  /*   Mode 1		      */
-#define SDRAM_BXCR_SDAM_2	0x00002000	  /*   Mode 2		      */
-#define SDRAM_BXCR_SDAM_3	0x00004000	  /*   Mode 3		      */
-#define SDRAM_BXCR_SDAM_4	0x00006000	  /*   Mode 4		      */
-#define SDRAM_BXCR_SDBE		0x00000001	  /* Memory Bank Enable	      */
-
-/*
- * SDRAM TR0 Options
- */
-#define SDRAM_TR0_SDWR_MASK	0x80000000
-#define	 SDRAM_TR0_SDWR_2_CLK	0x00000000
-#define	 SDRAM_TR0_SDWR_3_CLK	0x80000000
-#define SDRAM_TR0_SDWD_MASK	0x40000000
-#define	 SDRAM_TR0_SDWD_0_CLK	0x00000000
-#define	 SDRAM_TR0_SDWD_1_CLK	0x40000000
-#define SDRAM_TR0_SDCL_MASK	0x01800000
-#define	 SDRAM_TR0_SDCL_2_0_CLK 0x00800000
-#define	 SDRAM_TR0_SDCL_2_5_CLK 0x01000000
-#define	 SDRAM_TR0_SDCL_3_0_CLK 0x01800000
-#define SDRAM_TR0_SDPA_MASK	0x000C0000
-#define	 SDRAM_TR0_SDPA_2_CLK	0x00040000
-#define	 SDRAM_TR0_SDPA_3_CLK	0x00080000
-#define	 SDRAM_TR0_SDPA_4_CLK	0x000C0000
-#define SDRAM_TR0_SDCP_MASK	0x00030000
-#define	 SDRAM_TR0_SDCP_2_CLK	0x00000000
-#define	 SDRAM_TR0_SDCP_3_CLK	0x00010000
-#define	 SDRAM_TR0_SDCP_4_CLK	0x00020000
-#define	 SDRAM_TR0_SDCP_5_CLK	0x00030000
-#define SDRAM_TR0_SDLD_MASK	0x0000C000
-#define	 SDRAM_TR0_SDLD_1_CLK	0x00000000
-#define	 SDRAM_TR0_SDLD_2_CLK	0x00004000
-#define SDRAM_TR0_SDRA_MASK	0x0000001C
-#define	 SDRAM_TR0_SDRA_6_CLK	0x00000000
-#define	 SDRAM_TR0_SDRA_7_CLK	0x00000004
-#define	 SDRAM_TR0_SDRA_8_CLK	0x00000008
-#define	 SDRAM_TR0_SDRA_9_CLK	0x0000000C
-#define	 SDRAM_TR0_SDRA_10_CLK	0x00000010
-#define	 SDRAM_TR0_SDRA_11_CLK	0x00000014
-#define	 SDRAM_TR0_SDRA_12_CLK	0x00000018
-#define	 SDRAM_TR0_SDRA_13_CLK	0x0000001C
-#define SDRAM_TR0_SDRD_MASK	0x00000003
-#define	 SDRAM_TR0_SDRD_2_CLK	0x00000001
-#define	 SDRAM_TR0_SDRD_3_CLK	0x00000002
-#define	 SDRAM_TR0_SDRD_4_CLK	0x00000003
-
-/*
- * SDRAM TR1 Options
- */
-#define SDRAM_TR1_RDSS_MASK	0xC0000000
-#define	 SDRAM_TR1_RDSS_TR0	0x00000000
-#define	 SDRAM_TR1_RDSS_TR1	0x40000000
-#define	 SDRAM_TR1_RDSS_TR2	0x80000000
-#define	 SDRAM_TR1_RDSS_TR3	0xC0000000
-#define SDRAM_TR1_RDSL_MASK	0x00C00000
-#define	 SDRAM_TR1_RDSL_STAGE1	0x00000000
-#define	 SDRAM_TR1_RDSL_STAGE2	0x00400000
-#define	 SDRAM_TR1_RDSL_STAGE3	0x00800000
-#define SDRAM_TR1_RDCD_MASK	0x00000800
-#define	 SDRAM_TR1_RDCD_RCD_0_0 0x00000000
-#define	 SDRAM_TR1_RDCD_RCD_1_2 0x00000800
-#define SDRAM_TR1_RDCT_MASK	0x000001FF
-#define	 SDRAM_TR1_RDCT_ENCODE(x)  (((x) << 0) & SDRAM_TR1_RDCT_MASK)
-#define	 SDRAM_TR1_RDCT_DECODE(x)  (((x) & SDRAM_TR1_RDCT_MASK) >> 0)
-#define	 SDRAM_TR1_RDCT_MIN	0x00000000
-#define	 SDRAM_TR1_RDCT_MAX	0x000001FF
-
-/*
- * SDRAM WDDCTR Options
- */
-#define SDRAM_WDDCTR_WRCP_MASK	0xC0000000
-#define	 SDRAM_WDDCTR_WRCP_0DEG	  0x00000000
-#define	 SDRAM_WDDCTR_WRCP_90DEG  0x40000000
-#define	 SDRAM_WDDCTR_WRCP_180DEG 0x80000000
-#define SDRAM_WDDCTR_DCD_MASK	0x000001FF
-
-/*
- * SDRAM CLKTR Options
- */
-#define SDRAM_CLKTR_CLKP_MASK	0xC0000000
-#define	 SDRAM_CLKTR_CLKP_0DEG	  0x00000000
-#define	 SDRAM_CLKTR_CLKP_90DEG	  0x40000000
-#define	 SDRAM_CLKTR_CLKP_180DEG  0x80000000
-#define SDRAM_CLKTR_DCDT_MASK	0x000001FF
-
-/*
- * SDRAM DLYCAL Options
- */
-#define SDRAM_DLYCAL_DLCV_MASK	0x000003FC
-#define	 SDRAM_DLYCAL_DLCV_ENCODE(x) (((x)<<2) & SDRAM_DLYCAL_DLCV_MASK)
-#define	 SDRAM_DLYCAL_DLCV_DECODE(x) (((x) & SDRAM_DLYCAL_DLCV_MASK)>>2)
-
-#endif /* CONFIG_SDRAM_PPC4xx_IBM_DDR */
-
-#if defined(CONFIG_SDRAM_PPC4xx_IBM_DDR2)
-
-#define SDRAM_DLYCAL_DLCV_MASK		0x000003FC
-#define SDRAM_DLYCAL_DLCV_ENCODE(x)	(((x)<<2) & SDRAM_DLYCAL_DLCV_MASK)
-#define SDRAM_DLYCAL_DLCV_DECODE(x)	(((x) & SDRAM_DLYCAL_DLCV_MASK)>>2)
-
-#if !defined(CONFIG_405EX)
-/*
- * Memory queue defines
- */
-#define SDRAMQ_DCR_BASE 0x040
-
-#define SDRAM_R0BAS		(SDRAMQ_DCR_BASE+0x0)	/* rank 0 base address & size  */
-#define SDRAM_R1BAS		(SDRAMQ_DCR_BASE+0x1)	/* rank 1 base address & size  */
-#define SDRAM_R2BAS		(SDRAMQ_DCR_BASE+0x2)	/* rank 2 base address & size  */
-#define SDRAM_R3BAS		(SDRAMQ_DCR_BASE+0x3)	/* rank 3 base address & size  */
-#define SDRAM_CONF1HB		(SDRAMQ_DCR_BASE+0x5)	/* configuration 1 HB          */
-#define SDRAM_CONF1HB_AAFR	0x80000000	/* Address Ack on First Request - Bit 0 */
-#define SDRAM_CONF1HB_PRPD	0x00080000	/* PLB Read pipeline Disable - Bit 12 */
-#define SDRAM_CONF1HB_PWPD	0x00040000	/* PLB Write pipeline Disable - Bit 13 */
-#define SDRAM_CONF1HB_PRW	0x00020000	/* PLB Read Wait - Bit 14 */
-#define SDRAM_CONF1HB_RPLM	0x00001000	/* Read Passing Limit 1 - Bits 16..19 */
-#define SDRAM_CONF1HB_RPEN	0x00000800	/* Read Passing Enable - Bit 20 */
-#define SDRAM_CONF1HB_RFTE	0x00000400	/* Read Flow Through Enable - Bit 21 */
-#define SDRAM_CONF1HB_WRCL	0x00000080	/* MCIF Cycle Limit 1 - Bits 22..24 */
-#define SDRAM_CONF1HB_MASK	0x0000F380	/* RPLM & WRCL mask */
-
-#define SDRAM_ERRSTATHB		(SDRAMQ_DCR_BASE+0x7)	/* error status HB             */
-#define SDRAM_ERRADDUHB		(SDRAMQ_DCR_BASE+0x8)	/* error address upper 32 HB   */
-#define SDRAM_ERRADDLHB		(SDRAMQ_DCR_BASE+0x9)	/* error address lower 32 HB   */
-#define SDRAM_PLBADDULL		(SDRAMQ_DCR_BASE+0xA)	/* PLB base address upper 32 LL */
-#define SDRAM_CONF1LL		(SDRAMQ_DCR_BASE+0xB)	/* configuration 1 LL          */
-#define SDRAM_CONF1LL_AAFR	0x80000000		/* Address Ack on First Request - Bit 0 */
-#define SDRAM_CONF1LL_PRPD	0x00080000		/* PLB Read pipeline Disable - Bit 12 */
-#define SDRAM_CONF1LL_PWPD	0x00040000		/* PLB Write pipeline Disable - Bit 13 */
-#define SDRAM_CONF1LL_PRW	0x00020000		/* PLB Read Wait - Bit 14 */
-#define SDRAM_CONF1LL_RPLM	0x00001000		/* Read Passing Limit 1 - Bits 16..19 */
-#define SDRAM_CONF1LL_RPEN	0x00000800		/* Read Passing Enable - Bit 20 */
-#define SDRAM_CONF1LL_RFTE	0x00000400		/* Read Flow Through Enable - Bit 21 */
-#define SDRAM_CONF1LL_MASK	0x0000F000		/* RPLM mask */
-
-#define SDRAM_ERRSTATLL		(SDRAMQ_DCR_BASE+0xC)	/* error status LL             */
-#define SDRAM_ERRADDULL		(SDRAMQ_DCR_BASE+0xD)	/* error address upper 32 LL   */
-#define SDRAM_ERRADDLLL		(SDRAMQ_DCR_BASE+0xE)	/* error address lower 32 LL   */
-#define SDRAM_CONFPATHB		(SDRAMQ_DCR_BASE+0xF)	/* configuration between paths */
-#define SDRAM_CONFPATHB_TPEN	0x08000000		/* Transaction Passing Enable - Bit 4 */
-
-#define SDRAM_PLBADDUHB		(SDRAMQ_DCR_BASE+0x10)  /* PLB base address upper 32 LL */
-
-/*
- * Memory Bank 0-7 configuration
- */
-#if defined(CONFIG_440SPE) || \
-    defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
-    defined(CONFIG_460SX)
-#define SDRAM_RXBAS_SDBA_MASK		0xFFE00000	/* Base address	*/
-#define SDRAM_RXBAS_SDBA_ENCODE(n)	((u32)(((phys_size_t)(n) >> 2) & 0xFFE00000))
-#define SDRAM_RXBAS_SDBA_DECODE(n)	((((phys_size_t)(n)) & 0xFFE00000) << 2)
-#endif /* CONFIG_440SPE */
-#if defined(CONFIG_440SP)
-#define SDRAM_RXBAS_SDBA_MASK		0xFF800000	/* Base address	*/
-#define SDRAM_RXBAS_SDBA_ENCODE(n)	((((u32)(n))&0xFF800000))
-#define SDRAM_RXBAS_SDBA_DECODE(n)	((((u32)(n))&0xFF800000))
-#endif /* CONFIG_440SP */
-#define SDRAM_RXBAS_SDSZ_MASK		0x0000FFC0	/* Size		*/
-#define SDRAM_RXBAS_SDSZ_ENCODE(n)	((((u32)(n))&0x3FF)<<6)
-#define SDRAM_RXBAS_SDSZ_DECODE(n)	((((u32)(n))>>6)&0x3FF)
-#define SDRAM_RXBAS_SDSZ_0		0x00000000	/*   0M		*/
-#define SDRAM_RXBAS_SDSZ_8		0x0000FFC0	/*   8M		*/
-#define SDRAM_RXBAS_SDSZ_16		0x0000FF80	/*  16M		*/
-#define SDRAM_RXBAS_SDSZ_32		0x0000FF00	/*  32M		*/
-#define SDRAM_RXBAS_SDSZ_64		0x0000FE00	/*  64M		*/
-#define SDRAM_RXBAS_SDSZ_128		0x0000FC00	/* 128M		*/
-#define SDRAM_RXBAS_SDSZ_256		0x0000F800	/* 256M		*/
-#define SDRAM_RXBAS_SDSZ_512		0x0000F000	/* 512M		*/
-#define SDRAM_RXBAS_SDSZ_1024		0x0000E000	/* 1024M	*/
-#define SDRAM_RXBAS_SDSZ_2048		0x0000C000	/* 2048M	*/
-#define SDRAM_RXBAS_SDSZ_4096		0x00008000	/* 4096M	*/
-#else /* CONFIG_405EX */
-/*
- * XXX - ToDo:
- * Revisit this file to check if all these 405EX defines are correct and
- * can be used in the common 44x_spd_ddr2 code as well. sr, 2008-06-02
- */
-#define SDRAM_RXBAS_SDSZ_MASK		PPC_REG_VAL(19, 0xF)
-#define SDRAM_RXBAS_SDSZ_4MB	   	PPC_REG_VAL(19, 0x0)
-#define SDRAM_RXBAS_SDSZ_8MB	   	PPC_REG_VAL(19, 0x1)
-#define SDRAM_RXBAS_SDSZ_16MB	   	PPC_REG_VAL(19, 0x2)
-#define SDRAM_RXBAS_SDSZ_32MB	   	PPC_REG_VAL(19, 0x3)
-#define SDRAM_RXBAS_SDSZ_64MB	   	PPC_REG_VAL(19, 0x4)
-#define SDRAM_RXBAS_SDSZ_128MB	   	PPC_REG_VAL(19, 0x5)
-#define SDRAM_RXBAS_SDSZ_256MB	   	PPC_REG_VAL(19, 0x6)
-#define SDRAM_RXBAS_SDSZ_512MB	   	PPC_REG_VAL(19, 0x7)
-#define SDRAM_RXBAS_SDSZ_1024MB	   	PPC_REG_VAL(19, 0x8)
-#define SDRAM_RXBAS_SDSZ_2048MB	   	PPC_REG_VAL(19, 0x9)
-#define SDRAM_RXBAS_SDSZ_4096MB		PPC_REG_VAL(19, 0xA)
-#define SDRAM_RXBAS_SDSZ_8192MB		PPC_REG_VAL(19, 0xB)
-#define SDRAM_RXBAS_SDSZ_8      	SDRAM_RXBAS_SDSZ_8MB
-#define SDRAM_RXBAS_SDSZ_16     	SDRAM_RXBAS_SDSZ_16MB
-#define SDRAM_RXBAS_SDSZ_32     	SDRAM_RXBAS_SDSZ_32MB
-#define SDRAM_RXBAS_SDSZ_64     	SDRAM_RXBAS_SDSZ_64MB
-#define SDRAM_RXBAS_SDSZ_128    	SDRAM_RXBAS_SDSZ_128MB
-#define SDRAM_RXBAS_SDSZ_256    	SDRAM_RXBAS_SDSZ_256MB
-#define SDRAM_RXBAS_SDSZ_512    	SDRAM_RXBAS_SDSZ_512MB
-#define SDRAM_RXBAS_SDSZ_1024		SDRAM_RXBAS_SDSZ_1024MB
-#define SDRAM_RXBAS_SDSZ_2048		SDRAM_RXBAS_SDSZ_2048MB
-#define SDRAM_RXBAS_SDSZ_4096		SDRAM_RXBAS_SDSZ_4096MB
-#define SDRAM_RXBAS_SDSZ_8192		SDRAM_RXBAS_SDSZ_8192MB
-#endif /* CONFIG_405EX */
-
-/* The mode definitions are the same for all PPC4xx variants */
-#define SDRAM_RXBAS_SDAM_MODE0		PPC_REG_VAL(23, 0x0)
-#define SDRAM_RXBAS_SDAM_MODE1		PPC_REG_VAL(23, 0x1)
-#define SDRAM_RXBAS_SDAM_MODE2		PPC_REG_VAL(23, 0x2)
-#define SDRAM_RXBAS_SDAM_MODE3		PPC_REG_VAL(23, 0x3)
-#define SDRAM_RXBAS_SDAM_MODE4		PPC_REG_VAL(23, 0x4)
-#define SDRAM_RXBAS_SDAM_MODE5		PPC_REG_VAL(23, 0x5)
-#define SDRAM_RXBAS_SDAM_MODE6		PPC_REG_VAL(23, 0x6)
-#define SDRAM_RXBAS_SDAM_MODE7		PPC_REG_VAL(23, 0x7)
-#define SDRAM_RXBAS_SDAM_MODE8		PPC_REG_VAL(23, 0x8)
-#define SDRAM_RXBAS_SDAM_MODE9		PPC_REG_VAL(23, 0x9)
-#define SDRAM_RXBAS_SDBE_DISABLE	PPC_REG_VAL(31, 0x0)
-#define SDRAM_RXBAS_SDBE_ENABLE		PPC_REG_VAL(31, 0x1)
-
-/*
- * Memory controller registers
- */
-#if defined(CONFIG_405EX)
-#define SDRAM_BESR	0x00	/* PLB bus error status (read/clear)         */
-#define SDRAM_BESRT	0x01	/* PLB bus error status (test/set)           */
-#define SDRAM_BEARL	0x02	/* PLB bus error address low                 */
-#define SDRAM_BEARH	0x03	/* PLB bus error address high                */
-#define SDRAM_WMIRQ	0x06	/* PLB write master interrupt (read/clear)   */
-#define SDRAM_WMIRQT	0x07	/* PLB write master interrupt (test/set)     */
-#define SDRAM_PLBOPT	0x08	/* PLB slave options                         */
-#define SDRAM_PUABA	0x09	/* PLB upper address base                    */
-#define SDRAM_MCSTAT	0x1F	/* memory controller status                  */
-#else /* CONFIG_405EX */
-#define SDRAM_MCSTAT	0x14	/* memory controller status                  */
-#endif /* CONFIG_405EX */
-#define SDRAM_MCOPT1	0x20	/* memory controller options 1               */
-#define SDRAM_MCOPT2	0x21	/* memory controller options 2               */
-#define SDRAM_MODT0	0x22	/* on die termination for bank 0             */
-#define SDRAM_MODT1	0x23	/* on die termination for bank 1             */
-#define SDRAM_MODT2	0x24	/* on die termination for bank 2             */
-#define SDRAM_MODT3	0x25	/* on die termination for bank 3             */
-#define SDRAM_CODT	0x26	/* on die termination for controller         */
-#define SDRAM_VVPR	0x27	/* variable VRef programmming                */
-#define SDRAM_OPARS	0x28	/* on chip driver control setup              */
-#define SDRAM_OPART	0x29	/* on chip driver control trigger            */
-#define SDRAM_RTR	0x30	/* refresh timer                             */
-#define SDRAM_PMIT	0x34	/* power management idle timer               */
-#define SDRAM_MB0CF	0x40	/* memory bank 0 configuration               */
-#define SDRAM_MB1CF	0x44	/* memory bank 1 configuration               */
-#define SDRAM_MB2CF	0x48
-#define SDRAM_MB3CF	0x4C
-#define SDRAM_INITPLR0	0x50	/* manual initialization control             */
-#define SDRAM_INITPLR1	0x51	/* manual initialization control             */
-#define SDRAM_INITPLR2	0x52	/* manual initialization control             */
-#define SDRAM_INITPLR3	0x53	/* manual initialization control             */
-#define SDRAM_INITPLR4	0x54	/* manual initialization control             */
-#define SDRAM_INITPLR5	0x55	/* manual initialization control             */
-#define SDRAM_INITPLR6	0x56	/* manual initialization control             */
-#define SDRAM_INITPLR7	0x57	/* manual initialization control             */
-#define SDRAM_INITPLR8	0x58	/* manual initialization control             */
-#define SDRAM_INITPLR9	0x59	/* manual initialization control             */
-#define SDRAM_INITPLR10	0x5a	/* manual initialization control             */
-#define SDRAM_INITPLR11	0x5b	/* manual initialization control             */
-#define SDRAM_INITPLR12	0x5c	/* manual initialization control             */
-#define SDRAM_INITPLR13	0x5d	/* manual initialization control             */
-#define SDRAM_INITPLR14	0x5e	/* manual initialization control             */
-#define SDRAM_INITPLR15	0x5f	/* manual initialization control             */
-#define SDRAM_RQDC	0x70	/* read DQS delay control                    */
-#define SDRAM_RFDC	0x74	/* read feedback delay control               */
-#define SDRAM_RDCC	0x78	/* read data capture control                 */
-#define SDRAM_DLCR	0x7A	/* delay line calibration                    */
-#define SDRAM_CLKTR	0x80	/* DDR clock timing                          */
-#define SDRAM_WRDTR	0x81	/* write data, DQS, DM clock, timing         */
-#define SDRAM_SDTR1	0x85	/* DDR SDRAM timing 1                        */
-#define SDRAM_SDTR2	0x86	/* DDR SDRAM timing 2                        */
-#define SDRAM_SDTR3	0x87	/* DDR SDRAM timing 3                        */
-#define SDRAM_MMODE	0x88	/* memory mode                               */
-#define SDRAM_MEMODE	0x89	/* memory extended mode                      */
-#define SDRAM_ECCES	0x98	/* ECC error status                          */
-#define SDRAM_CID	0xA4	/* core ID                                   */
-#if !defined(CONFIG_405EX)
-#define SDRAM_RID	0xA8	/* revision ID                               */
-#endif
-#define SDRAM_FCSR	0xB0	/* feedback calibration status               */
-#define SDRAM_RTSR	0xB1	/* run time status tracking                  */
-#if  defined(CONFIG_405EX)
-#define SDRAM_RID	0xF8	/* revision ID                               */
-#endif
-
-/*
- * Memory Controller Bus Error Status
- */
-#define SDRAM_BESR_MASK			PPC_REG_VAL(7, 0xFF)
-#define SDRAM_BESR_M0ID_MASK		PPC_REG_VAL(3, 0xF)
-#define SDRAM_BESR_M0ID_ICU		PPC_REG_VAL(3, 0x0)
-#define SDRAM_BESR_M0ID_PCIE0		PPC_REG_VAL(3, 0x1)
-#define SDRAM_BESR_M0ID_PCIE1		PPC_REG_VAL(3, 0x2)
-#define SDRAM_BESR_M0ID_DMA		PPC_REG_VAL(3, 0x3)
-#define SDRAM_BESR_M0ID_DCU		PPC_REG_VAL(3, 0x4)
-#define SDRAM_BESR_M0ID_OPB		PPC_REG_VAL(3, 0x5)
-#define SDRAM_BESR_M0ID_MAL		PPC_REG_VAL(3, 0x6)
-#define SDRAM_BESR_M0ID_SEC		PPC_REG_VAL(3, 0x7)
-#define SDRAM_BESR_M0ET_MASK		PPC_REG_VAL(6, 0x7)
-#define SDRAM_BESR_M0ET_NONE		PPC_REG_VAL(6, 0x0)
-#define SDRAM_BESR_M0ET_ECC		PPC_REG_VAL(6, 0x1)
-#define SDRAM_BESR_M0RW_WRITE		PPC_REG_VAL(7, 0)
-#define SDRAM_BESR_M0RW_READ		PPC_REG_VAL(8, 1)
-
-/*
- * Memory Controller Status
- */
-#define SDRAM_MCSTAT_MIC_MASK		0x80000000	/* Memory init status mask	*/
-#define SDRAM_MCSTAT_MIC_NOTCOMP	0x00000000	/* Mem init not complete	*/
-#define SDRAM_MCSTAT_MIC_COMP		0x80000000	/* Mem init complete		*/
-#define SDRAM_MCSTAT_SRMS_MASK		0x40000000	/* Mem self refresh stat mask	*/
-#define SDRAM_MCSTAT_SRMS_NOT_SF	0x00000000	/* Mem not in self refresh	*/
-#define SDRAM_MCSTAT_SRMS_SF		0x40000000	/* Mem in self refresh		*/
-#define SDRAM_MCSTAT_IDLE_MASK		0x20000000	/* Mem self refresh stat mask	*/
-#define SDRAM_MCSTAT_IDLE_NOT		0x00000000	/* Mem contr not idle		*/
-#define SDRAM_MCSTAT_IDLE		0x20000000	/* Mem contr idle		*/
-
-/*
- * Memory Controller Options 1
- */
-#define SDRAM_MCOPT1_MCHK_MASK		0x30000000 /* Memory data err check mask*/
-#define SDRAM_MCOPT1_MCHK_NON		0x00000000 /* No ECC generation		*/
-#define SDRAM_MCOPT1_MCHK_GEN		0x20000000 /* ECC generation		*/
-#define SDRAM_MCOPT1_MCHK_CHK		0x10000000 /* ECC generation and check	*/
-#define SDRAM_MCOPT1_MCHK_CHK_REP	0x30000000 /* ECC generation, chk, report*/
-#define SDRAM_MCOPT1_MCHK_CHK_DECODE(n)	((((u32)(n))>>28)&0x3)
-#define SDRAM_MCOPT1_RDEN_MASK		0x08000000 /* Registered DIMM mask	*/
-#define SDRAM_MCOPT1_RDEN		0x08000000 /* Registered DIMM enable	*/
-#define SDRAM_MCOPT1_PMU_MASK		0x06000000 /* Page management unit mask	*/
-#define SDRAM_MCOPT1_PMU_CLOSE		0x00000000 /* PMU Close			*/
-#define SDRAM_MCOPT1_PMU_OPEN		0x04000000 /* PMU Open			*/
-#define SDRAM_MCOPT1_PMU_AUTOCLOSE	0x02000000 /* PMU AutoClose		*/
-#define SDRAM_MCOPT1_DMWD_MASK		0x01000000 /* DRAM width mask		*/
-#define SDRAM_MCOPT1_DMWD_32		0x00000000 /* 32 bits			*/
-#define SDRAM_MCOPT1_DMWD_64		0x01000000 /* 64 bits			*/
-#define SDRAM_MCOPT1_UIOS_MASK		0x00C00000 /* Unused IO State		*/
-#define SDRAM_MCOPT1_BCNT_MASK		0x00200000 /* Bank count		*/
-#define SDRAM_MCOPT1_4_BANKS		0x00000000 /* 4 Banks			*/
-#define SDRAM_MCOPT1_8_BANKS		0x00200000 /* 8 Banks			*/
-#define SDRAM_MCOPT1_DDR_TYPE_MASK	0x00100000 /* DDR Memory Type mask	*/
-#define SDRAM_MCOPT1_DDR1_TYPE		0x00000000 /* DDR1 Memory Type		*/
-#define SDRAM_MCOPT1_DDR2_TYPE		0x00100000 /* DDR2 Memory Type		*/
-#define SDRAM_MCOPT1_QDEP		0x00020000 /* 4 commands deep		*/
-#define SDRAM_MCOPT1_RWOO_MASK		0x00008000 /* Out of Order Read mask	*/
-#define SDRAM_MCOPT1_RWOO_DISABLED	0x00000000 /* disabled			*/
-#define SDRAM_MCOPT1_RWOO_ENABLED	0x00008000 /* enabled			*/
-#define SDRAM_MCOPT1_WOOO_MASK		0x00004000 /* Out of Order Write mask	*/
-#define SDRAM_MCOPT1_WOOO_DISABLED	0x00000000 /* disabled			*/
-#define SDRAM_MCOPT1_WOOO_ENABLED	0x00004000 /* enabled			*/
-#define SDRAM_MCOPT1_DCOO_MASK		0x00002000 /* All Out of Order mask	*/
-#define SDRAM_MCOPT1_DCOO_DISABLED	0x00002000 /* disabled			*/
-#define SDRAM_MCOPT1_DCOO_ENABLED	0x00000000 /* enabled			*/
-#define SDRAM_MCOPT1_DREF_MASK		0x00001000 /* Deferred refresh mask	*/
-#define SDRAM_MCOPT1_DREF_NORMAL	0x00000000 /* normal refresh		*/
-#define SDRAM_MCOPT1_DREF_DEFER_4	0x00001000 /* defer up to 4 refresh cmd	*/
-
-/*
- * Memory Controller Options 2
- */
-#define SDRAM_MCOPT2_SREN_MASK		0x80000000 /* Self Test mask		*/
-#define SDRAM_MCOPT2_SREN_EXIT		0x00000000 /* Self Test exit		*/
-#define SDRAM_MCOPT2_SREN_ENTER		0x80000000 /* Self Test enter		*/
-#define SDRAM_MCOPT2_PMEN_MASK		0x40000000 /* Power Management mask	*/
-#define SDRAM_MCOPT2_PMEN_DISABLE	0x00000000 /* disable			*/
-#define SDRAM_MCOPT2_PMEN_ENABLE	0x40000000 /* enable			*/
-#define SDRAM_MCOPT2_IPTR_MASK		0x20000000 /* Init Trigger Reg mask	*/
-#define SDRAM_MCOPT2_IPTR_IDLE		0x00000000 /* idle			*/
-#define SDRAM_MCOPT2_IPTR_EXECUTE	0x20000000 /* execute preloaded init	*/
-#define SDRAM_MCOPT2_XSRP_MASK		0x10000000 /* Exit Self Refresh Prevent	*/
-#define SDRAM_MCOPT2_XSRP_ALLOW		0x00000000 /* allow self refresh exit	*/
-#define SDRAM_MCOPT2_XSRP_PREVENT	0x10000000 /* prevent self refresh exit	*/
-#define SDRAM_MCOPT2_DCEN_MASK		0x08000000 /* SDRAM Controller Enable	*/
-#define SDRAM_MCOPT2_DCEN_DISABLE	0x00000000 /* SDRAM Controller Enable	*/
-#define SDRAM_MCOPT2_DCEN_ENABLE	0x08000000 /* SDRAM Controller Enable	*/
-#define SDRAM_MCOPT2_ISIE_MASK		0x04000000 /* Init Seq Interruptable mas*/
-#define SDRAM_MCOPT2_ISIE_DISABLE	0x00000000 /* disable			*/
-#define SDRAM_MCOPT2_ISIE_ENABLE	0x04000000 /* enable			*/
-
-/*
- * SDRAM Refresh Timer Register
- */
-#define SDRAM_RTR_RINT_MASK		0xFFF80000
-#define SDRAM_RTR_RINT_ENCODE(n)	((((u32)(n))&0xFFF8)<<16)
-#define SDRAM_RTR_RINT_DECODE(n)	((((u32)(n))>>16)&0xFFF8)
-
-/*
- * SDRAM Read DQS Delay Control Register
- */
-#define SDRAM_RQDC_RQDE_MASK		0x80000000
-#define SDRAM_RQDC_RQDE_DISABLE		0x00000000
-#define SDRAM_RQDC_RQDE_ENABLE		0x80000000
-#define SDRAM_RQDC_RQFD_MASK		0x000001FF
-#define SDRAM_RQDC_RQFD_ENCODE(n)	((((u32)(n))&0x1FF)<<0)
-
-#define SDRAM_RQDC_RQFD_MAX		0x1FF
-
-/*
- * SDRAM Read Data Capture Control Register
- */
-#define SDRAM_RDCC_RDSS_MASK		0xC0000000
-#define SDRAM_RDCC_RDSS_T1		0x00000000
-#define SDRAM_RDCC_RDSS_T2		0x40000000
-#define SDRAM_RDCC_RDSS_T3		0x80000000
-#define SDRAM_RDCC_RDSS_T4		0xC0000000
-#define SDRAM_RDCC_RSAE_MASK		0x00000001
-#define SDRAM_RDCC_RSAE_DISABLE		0x00000001
-#define SDRAM_RDCC_RSAE_ENABLE		0x00000000
-#define SDRAM_RDCC_RDSS_ENCODE(n)	((((u32)(n))&0x03)<<30)
-#define SDRAM_RDCC_RDSS_DECODE(n)	((((u32)(n))>>30)&0x03)
-
-/*
- * SDRAM Read Feedback Delay Control Register
- */
-#define SDRAM_RFDC_ARSE_MASK		0x80000000
-#define SDRAM_RFDC_ARSE_DISABLE		0x80000000
-#define SDRAM_RFDC_ARSE_ENABLE		0x00000000
-#define SDRAM_RFDC_RFOS_MASK		0x007F0000
-#define SDRAM_RFDC_RFOS_ENCODE(n)	((((u32)(n))&0x7F)<<16)
-#define SDRAM_RFDC_RFFD_MASK		0x000007FF
-#define SDRAM_RFDC_RFFD_ENCODE(n)	((((u32)(n))&0x7FF)<<0)
-
-#define SDRAM_RFDC_RFFD_MAX		0x7FF
-
-/*
- * SDRAM Delay Line Calibration Register
- */
-#define SDRAM_DLCR_DCLM_MASK		0x80000000
-#define SDRAM_DLCR_DCLM_MANUAL		0x80000000
-#define SDRAM_DLCR_DCLM_AUTO		0x00000000
-#define SDRAM_DLCR_DLCR_MASK		0x08000000
-#define SDRAM_DLCR_DLCR_CALIBRATE	0x08000000
-#define SDRAM_DLCR_DLCR_IDLE		0x00000000
-#define SDRAM_DLCR_DLCS_MASK		0x07000000
-#define SDRAM_DLCR_DLCS_NOT_RUN		0x00000000
-#define SDRAM_DLCR_DLCS_IN_PROGRESS	0x01000000
-#define SDRAM_DLCR_DLCS_COMPLETE	0x02000000
-#define SDRAM_DLCR_DLCS_CONT_DONE	0x03000000
-#define SDRAM_DLCR_DLCS_ERROR		0x04000000
-#define SDRAM_DLCR_DLCV_MASK		0x000001FF
-#define SDRAM_DLCR_DLCV_ENCODE(n)	((((u32)(n))&0x1FF)<<0)
-#define SDRAM_DLCR_DLCV_DECODE(n)	((((u32)(n))>>0)&0x1FF)
-
-/*
- * SDRAM Memory On Die Terimination Control Register
- */
-#define SDRAM_MODT_ODTON_DISABLE		PPC_REG_VAL(0, 0)
-#define SDRAM_MODT_ODTON_ENABLE			PPC_REG_VAL(0, 1)
-#define SDRAM_MODT_EB1W_DISABLE			PPC_REG_VAL(1, 0)
-#define SDRAM_MODT_EB1W_ENABLE			PPC_REG_VAL(1, 1)
-#define SDRAM_MODT_EB1R_DISABLE			PPC_REG_VAL(2, 0)
-#define SDRAM_MODT_EB1R_ENABLE			PPC_REG_VAL(2, 1)
-#define SDRAM_MODT_EB0W_DISABLE			PPC_REG_VAL(7, 0)
-#define SDRAM_MODT_EB0W_ENABLE			PPC_REG_VAL(7, 1)
-#define SDRAM_MODT_EB0R_DISABLE			PPC_REG_VAL(8, 0)
-#define SDRAM_MODT_EB0R_ENABLE			PPC_REG_VAL(8, 1)
-
-/*
- * SDRAM Controller On Die Termination Register
- */
-#define SDRAM_CODT_ODT_ON			PPC_REG_VAL(0, 1)
-#define SDRAM_CODT_ODT_OFF			PPC_REG_VAL(0, 0)
-#define SDRAM_CODT_RK1W_ON			PPC_REG_VAL(1, 1)
-#define SDRAM_CODT_RK1W_OFF			PPC_REG_VAL(1, 0)
-#define SDRAM_CODT_RK1R_ON			PPC_REG_VAL(2, 1)
-#define SDRAM_CODT_RK1R_OFF			PPC_REG_VAL(2, 0)
-#define SDRAM_CODT_RK0W_ON			PPC_REG_VAL(7, 1)
-#define SDRAM_CODT_RK0W_OFF			PPC_REG_VAL(7, 0)
-#define SDRAM_CODT_RK0R_ON			PPC_REG_VAL(8, 1)
-#define SDRAM_CODT_RK0R_OFF			PPC_REG_VAL(8, 0)
-#define SDRAM_CODT_ODTSH_NORMAL			PPC_REG_VAL(10, 0)
-#define SDRAM_CODT_ODTSH_REMOVE_ONE_AT_END	PPC_REG_VAL(10, 1)
-#define SDRAM_CODT_ODTSH_ADD_ONE_AT_START	PPC_REG_VAL(10, 2)
-#define SDRAM_CODT_ODTSH_SHIFT_ONE_EARLIER	PPC_REG_VAL(10, 3)
-#define SDRAM_CODT_CODTZ_75OHM			PPC_REG_VAL(11, 0)
-#define SDRAM_CODT_CKEG_ON			PPC_REG_VAL(12, 1)
-#define SDRAM_CODT_CKEG_OFF			PPC_REG_VAL(12, 0)
-#define SDRAM_CODT_CTLG_ON			PPC_REG_VAL(13, 1)
-#define SDRAM_CODT_CTLG_OFF			PPC_REG_VAL(13, 0)
-#define SDRAM_CODT_FBDG_ON			PPC_REG_VAL(14, 1)
-#define SDRAM_CODT_FBDG_OFF			PPC_REG_VAL(14, 0)
-#define SDRAM_CODT_FBRG_ON			PPC_REG_VAL(15, 1)
-#define SDRAM_CODT_FBRG_OFF			PPC_REG_VAL(15, 0)
-#define SDRAM_CODT_CKLZ_36OHM			PPC_REG_VAL(18, 1)
-#define SDRAM_CODT_CKLZ_18OHM			PPC_REG_VAL(18, 0)
-#define SDRAM_CODT_DQS_VOLTAGE_DDR_MASK		PPC_REG_VAL(26, 1)
-#define SDRAM_CODT_DQS_2_5_V_DDR1		PPC_REG_VAL(26, 0)
-#define SDRAM_CODT_DQS_1_8_V_DDR2		PPC_REG_VAL(26, 1)
-#define SDRAM_CODT_DQS_MASK			PPC_REG_VAL(27, 1)
-#define SDRAM_CODT_DQS_DIFFERENTIAL		PPC_REG_VAL(27, 0)
-#define SDRAM_CODT_DQS_SINGLE_END		PPC_REG_VAL(27, 1)
-#define SDRAM_CODT_CKSE_DIFFERENTIAL		PPC_REG_VAL(28, 0)
-#define SDRAM_CODT_CKSE_SINGLE_END		PPC_REG_VAL(28, 1)
-#define SDRAM_CODT_FEEBBACK_RCV_SINGLE_END	PPC_REG_VAL(29, 1)
-#define SDRAM_CODT_FEEBBACK_DRV_SINGLE_END	PPC_REG_VAL(30, 1)
-#define SDRAM_CODT_IO_HIZ			PPC_REG_VAL(31, 0)
-#define SDRAM_CODT_IO_NMODE			PPC_REG_VAL(31, 1)
-
-/*
- * SDRAM Initialization Preload Register
- */
-#define SDRAM_INITPLR_ENABLE			PPC_REG_VAL(0, 1)
-#define SDRAM_INITPLR_DISABLE			PPC_REG_VAL(0, 0)
-#define SDRAM_INITPLR_IMWT_MASK			PPC_REG_VAL(8, 0xFF)
-#define SDRAM_INITPLR_IMWT_ENCODE(n)		PPC_REG_VAL(8, \
-							    (static_cast(u32, \
-									 n)) \
-							    & 0xFF)
-#define SDRAM_INITPLR_ICMD_MASK			PPC_REG_VAL(12, 0x7)
-#define SDRAM_INITPLR_ICMD_ENCODE(n)		PPC_REG_VAL(12, \
-							    (static_cast(u32, \
-									 n)) \
-							    & 0x7)
-#define SDRAM_INITPLR_IBA_MASK			PPC_REG_VAL(15, 0x7)
-#define SDRAM_INITPLR_IBA_ENCODE(n)		PPC_REG_VAL(15, \
-							    (static_cast(u32, \
-									 n)) \
-							    & 0x7)
-#define SDRAM_INITPLR_IMA_MASK			PPC_REG_VAL(31, 0x7FFF)
-#define SDRAM_INITPLR_IMA_ENCODE(n)		PPC_REG_VAL(31, \
-							    (static_cast(u32, \
-									 n)) \
-							    & 0x7FFF)
-
-/*
- * JEDEC DDR Initialization Commands
- */
-#define JEDEC_CMD_NOP				7
-#define JEDEC_CMD_PRECHARGE			2
-#define JEDEC_CMD_REFRESH			1
-#define JEDEC_CMD_EMR				0
-#define JEDEC_CMD_READ				5
-#define JEDEC_CMD_WRITE				4
-
-/*
- * JEDEC Precharge Command Memory Address Arguments
- */
-#define JEDEC_MA_PRECHARGE_ONE			(0 << 10)
-#define JEDEC_MA_PRECHARGE_ALL			(1 << 10)
-
-/*
- * JEDEC DDR EMR Command Bank Address Arguments
- */
-#define JEDEC_BA_MR				0
-#define JEDEC_BA_EMR				1
-#define JEDEC_BA_EMR2				2
-#define JEDEC_BA_EMR3				3
-
-/*
- * JEDEC DDR Mode Register
- */
-#define JEDEC_MA_MR_PDMODE_FAST_EXIT		(0 << 12)
-#define JEDEC_MA_MR_PDMODE_SLOW_EXIT		(1 << 12)
-#define JEDEC_MA_MR_WR_MASK			(0x7 << 9)
-#define JEDEC_MA_MR_WR_DDR1			(0x0 << 9)
-#define JEDEC_MA_MR_WR_DDR2_2_CYC		(0x1 << 9)
-#define JEDEC_MA_MR_WR_DDR2_3_CYC		(0x2 << 9)
-#define JEDEC_MA_MR_WR_DDR2_4_CYC		(0x3 << 9)
-#define JEDEC_MA_MR_WR_DDR2_5_CYC		(0x4 << 9)
-#define JEDEC_MA_MR_WR_DDR2_6_CYC		(0x5 << 9)
-#define JEDEC_MA_MR_DLL_RESET			(1 << 8)
-#define JEDEC_MA_MR_MODE_NORMAL			(0 << 8)
-#define JEDEC_MA_MR_MODE_TEST			(1 << 8)
-#define JEDEC_MA_MR_CL_MASK			(0x7 << 4)
-#define JEDEC_MA_MR_CL_DDR1_2_0_CLK		(0x2 << 4)
-#define JEDEC_MA_MR_CL_DDR1_2_5_CLK		(0x6 << 4)
-#define JEDEC_MA_MR_CL_DDR1_3_0_CLK		(0x3 << 4)
-#define JEDEC_MA_MR_CL_DDR2_2_0_CLK		(0x2 << 4)
-#define JEDEC_MA_MR_CL_DDR2_3_0_CLK		(0x3 << 4)
-#define JEDEC_MA_MR_CL_DDR2_4_0_CLK		(0x4 << 4)
-#define JEDEC_MA_MR_CL_DDR2_5_0_CLK		(0x5 << 4)
-#define JEDEC_MA_MR_CL_DDR2_6_0_CLK		(0x6 << 4)
-#define JEDEC_MA_MR_CL_DDR2_7_0_CLK		(0x7 << 4)
-#define JEDEC_MA_MR_BTYP_SEQUENTIAL		(0 << 3)
-#define JEDEC_MA_MR_BTYP_INTERLEAVED		(1 << 3)
-#define JEDEC_MA_MR_BLEN_MASK			(0x7 << 0)
-#define JEDEC_MA_MR_BLEN_4			(2 << 0)
-#define JEDEC_MA_MR_BLEN_8			(3 << 0)
-
-/*
- * JEDEC DDR Extended Mode Register
- */
-#define JEDEC_MA_EMR_OUTPUT_MASK		(1 << 12)
-#define JEDEC_MA_EMR_OUTPUT_ENABLE		(0 << 12)
-#define JEDEC_MA_EMR_OUTPUT_DISABLE		(1 << 12)
-#define JEDEC_MA_EMR_RQDS_MASK			(1 << 11)
-#define JEDEC_MA_EMR_RDQS_DISABLE		(0 << 11)
-#define JEDEC_MA_EMR_RDQS_ENABLE		(1 << 11)
-#define JEDEC_MA_EMR_DQS_MASK			(1 << 10)
-#define JEDEC_MA_EMR_DQS_DISABLE		(1 << 10)
-#define JEDEC_MA_EMR_DQS_ENABLE			(0 << 10)
-#define JEDEC_MA_EMR_OCD_MASK			(0x7 << 7)
-#define JEDEC_MA_EMR_OCD_EXIT			(0 << 7)
-#define JEDEC_MA_EMR_OCD_ENTER			(7 << 7)
-#define JEDEC_MA_EMR_AL_DDR1_0_CYC		(0 << 3)
-#define JEDEC_MA_EMR_AL_DDR2_1_CYC		(1 << 3)
-#define JEDEC_MA_EMR_AL_DDR2_2_CYC		(2 << 3)
-#define JEDEC_MA_EMR_AL_DDR2_3_CYC		(3 << 3)
-#define JEDEC_MA_EMR_AL_DDR2_4_CYC		(4 << 3)
-#define JEDEC_MA_EMR_RTT_MASK			(0x11 << 2)
-#define JEDEC_MA_EMR_RTT_DISABLED		(0x00 << 2)
-#define JEDEC_MA_EMR_RTT_75OHM			(0x01 << 2)
-#define JEDEC_MA_EMR_RTT_150OHM			(0x10 << 2)
-#define JEDEC_MA_EMR_RTT_50OHM			(0x11 << 2)
-#define JEDEC_MA_EMR_ODS_MASK			(1 << 1)
-#define JEDEC_MA_EMR_ODS_NORMAL			(0 << 1)
-#define JEDEC_MA_EMR_ODS_WEAK			(1 << 1)
-#define JEDEC_MA_EMR_DLL_MASK			(1 << 0)
-#define JEDEC_MA_EMR_DLL_ENABLE			(0 << 0)
-#define JEDEC_MA_EMR_DLL_DISABLE		(1 << 0)
-
-/*
- * JEDEC DDR Extended Mode Register 2
- */
-#define JEDEC_MA_EMR2_TEMP_COMMERCIAL		(0 << 7)
-#define JEDEC_MA_EMR2_TEMP_INDUSTRIAL		(1 << 7)
-
-/*
- * SDRAM Mode Register (Corresponds 1:1 w/ JEDEC Mode Register)
- */
-#define SDRAM_MMODE_WR_MASK			JEDEC_MA_MR_WR_MASK
-#define SDRAM_MMODE_WR_DDR1			JEDEC_MA_MR_WR_DDR1
-#define SDRAM_MMODE_WR_DDR2_2_CYC		JEDEC_MA_MR_WR_DDR2_2_CYC
-#define SDRAM_MMODE_WR_DDR2_3_CYC		JEDEC_MA_MR_WR_DDR2_3_CYC
-#define SDRAM_MMODE_WR_DDR2_4_CYC		JEDEC_MA_MR_WR_DDR2_4_CYC
-#define SDRAM_MMODE_WR_DDR2_5_CYC		JEDEC_MA_MR_WR_DDR2_5_CYC
-#define SDRAM_MMODE_WR_DDR2_6_CYC		JEDEC_MA_MR_WR_DDR2_6_CYC
-#define SDRAM_MMODE_DCL_MASK			JEDEC_MA_MR_CL_MASK
-#define SDRAM_MMODE_DCL_DDR1_2_0_CLK		JEDEC_MA_MR_CL_DDR1_2_0_CLK
-#define SDRAM_MMODE_DCL_DDR1_2_5_CLK		JEDEC_MA_MR_CL_DDR1_2_5_CLK
-#define SDRAM_MMODE_DCL_DDR1_3_0_CLK		JEDEC_MA_MR_CL_DDR1_3_0_CLK
-#define SDRAM_MMODE_DCL_DDR2_2_0_CLK		JEDEC_MA_MR_CL_DDR2_2_0_CLK
-#define SDRAM_MMODE_DCL_DDR2_3_0_CLK		JEDEC_MA_MR_CL_DDR2_3_0_CLK
-#define SDRAM_MMODE_DCL_DDR2_4_0_CLK		JEDEC_MA_MR_CL_DDR2_4_0_CLK
-#define SDRAM_MMODE_DCL_DDR2_5_0_CLK		JEDEC_MA_MR_CL_DDR2_5_0_CLK
-#define SDRAM_MMODE_DCL_DDR2_6_0_CLK		JEDEC_MA_MR_CL_DDR2_6_0_CLK
-#define SDRAM_MMODE_DCL_DDR2_7_0_CLK		JEDEC_MA_MR_CL_DDR2_7_0_CLK
-#define SDRAM_MMODE_BTYP_SEQUENTIAL		JEDEC_MA_MR_BTYP_SEQUENTIAL
-#define SDRAM_MMODE_BTYP_INTERLEAVED		JEDEC_MA_MR_BTYP_INTERLEAVED
-#define SDRAM_MMODE_BLEN_MASK			JEDEC_MA_MR_BLEN_MASK
-#define SDRAM_MMODE_BLEN_4			JEDEC_MA_MR_BLEN_4
-#define SDRAM_MMODE_BLEN_8			JEDEC_MA_MR_BLEN_8
-
-/*
- * SDRAM Extended Mode Register (Corresponds 1:1 w/ JEDEC Extended
- * Mode Register)
- */
-#define SDRAM_MEMODE_QOFF_MASK			JEDEC_MA_EMR_OUTPUT_MASK
-#define SDRAM_MEMODE_QOFF_DISABLE		JEDEC_MA_EMR_OUTPUT_DISABLE
-#define SDRAM_MEMODE_QOFF_ENABLE		JEDEC_MA_EMR_OUTPUT_ENABLE
-#define SDRAM_MEMODE_RDQS_MASK			JEDEC_MA_EMR_RQDS_MASK
-#define SDRAM_MEMODE_RDQS_DISABLE		JEDEC_MA_EMR_RDQS_DISABLE
-#define SDRAM_MEMODE_RDQS_ENABLE		JEDEC_MA_EMR_RDQS_ENABLE
-#define SDRAM_MEMODE_DQS_MASK			JEDEC_MA_EMR_DQS_MASK
-#define SDRAM_MEMODE_DQS_DISABLE		JEDEC_MA_EMR_DQS_DISABLE
-#define SDRAM_MEMODE_DQS_ENABLE			JEDEC_MA_EMR_DQS_ENABLE
-#define SDRAM_MEMODE_AL_DDR1_0_CYC		JEDEC_MA_EMR_AL_DDR1_0_CYC
-#define SDRAM_MEMODE_AL_DDR2_1_CYC		JEDEC_MA_EMR_AL_DDR2_1_CYC
-#define SDRAM_MEMODE_AL_DDR2_2_CYC		JEDEC_MA_EMR_AL_DDR2_2_CYC
-#define SDRAM_MEMODE_AL_DDR2_3_CYC		JEDEC_MA_EMR_AL_DDR2_3_CYC
-#define SDRAM_MEMODE_AL_DDR2_4_CYC		JEDEC_MA_EMR_AL_DDR2_4_CYC
-#define SDRAM_MEMODE_RTT_MASK			JEDEC_MA_EMR_RTT_MASK
-#define SDRAM_MEMODE_RTT_DISABLED		JEDEC_MA_EMR_RTT_DISABLED
-#define SDRAM_MEMODE_RTT_75OHM			JEDEC_MA_EMR_RTT_75OHM
-#define SDRAM_MEMODE_RTT_150OHM			JEDEC_MA_EMR_RTT_150OHM
-#define SDRAM_MEMODE_RTT_50OHM			JEDEC_MA_EMR_RTT_50OHM
-#define SDRAM_MEMODE_DIC_MASK			JEDEC_MA_EMR_ODS_MASK
-#define SDRAM_MEMODE_DIC_NORMAL			JEDEC_MA_EMR_ODS_NORMAL
-#define SDRAM_MEMODE_DIC_WEAK			JEDEC_MA_EMR_ODS_WEAK
-#define SDRAM_MEMODE_DLL_MASK			JEDEC_MA_EMR_DLL_MASK
-#define SDRAM_MEMODE_DLL_DISABLE		JEDEC_MA_EMR_DLL_DISABLE
-#define SDRAM_MEMODE_DLL_ENABLE			JEDEC_MA_EMR_DLL_ENABLE
-
-/*
- * SDRAM Clock Timing Register
- */
-#define SDRAM_CLKTR_CLKP_MASK		0xC0000000
-#define SDRAM_CLKTR_CLKP_0_DEG		0x00000000
-#define SDRAM_CLKTR_CLKP_180_DEG_ADV	0x80000000
-#define SDRAM_CLKTR_CLKP_90_DEG_ADV	0x40000000
-#define SDRAM_CLKTR_CLKP_270_DEG_ADV	0xC0000000
-
-/*
- * SDRAM Write Timing Register
- */
-#define SDRAM_WRDTR_LLWP_MASK		0x10000000
-#define SDRAM_WRDTR_LLWP_DIS		0x10000000
-#define SDRAM_WRDTR_LLWP_1_CYC		0x00000000
-#define SDRAM_WRDTR_WTR_MASK		0x0E000000
-#define SDRAM_WRDTR_WTR_0_DEG		0x06000000
-#define SDRAM_WRDTR_WTR_90_DEG_ADV	0x04000000
-#define SDRAM_WRDTR_WTR_180_DEG_ADV	0x02000000
-#define SDRAM_WRDTR_WTR_270_DEG_ADV	0x00000000
-
-/*
- * SDRAM SDTR1 Options
- */
-#define SDRAM_SDTR1_LDOF_MASK		0x80000000
-#define SDRAM_SDTR1_LDOF_1_CLK		0x00000000
-#define SDRAM_SDTR1_LDOF_2_CLK		0x80000000
-#define SDRAM_SDTR1_RTW_MASK		0x00F00000
-#define SDRAM_SDTR1_RTW_2_CLK		0x00200000
-#define SDRAM_SDTR1_RTW_3_CLK		0x00300000
-#define SDRAM_SDTR1_WTWO_MASK		0x000F0000
-#define SDRAM_SDTR1_WTWO_0_CLK		0x00000000
-#define SDRAM_SDTR1_WTWO_1_CLK		0x00010000
-#define SDRAM_SDTR1_RTRO_MASK		0x0000F000
-#define SDRAM_SDTR1_RTRO_1_CLK		0x00001000
-#define SDRAM_SDTR1_RTRO_2_CLK		0x00002000
-
-/*
- * SDRAM SDTR2 Options
- */
-#define SDRAM_SDTR2_RCD_MASK		0xF0000000
-#define SDRAM_SDTR2_RCD_1_CLK		0x10000000
-#define SDRAM_SDTR2_RCD_2_CLK		0x20000000
-#define SDRAM_SDTR2_RCD_3_CLK		0x30000000
-#define SDRAM_SDTR2_RCD_4_CLK		0x40000000
-#define SDRAM_SDTR2_RCD_5_CLK		0x50000000
-#define SDRAM_SDTR2_WTR_MASK		0x0F000000
-#define SDRAM_SDTR2_WTR_1_CLK		0x01000000
-#define SDRAM_SDTR2_WTR_2_CLK		0x02000000
-#define SDRAM_SDTR2_WTR_3_CLK		0x03000000
-#define SDRAM_SDTR2_WTR_4_CLK		0x04000000
-#define SDRAM_SDTR3_WTR_ENCODE(n)	((((u32)(n))&0xF)<<24)
-#define SDRAM_SDTR2_XSNR_MASK		0x00FF0000
-#define SDRAM_SDTR2_XSNR_8_CLK		0x00080000
-#define SDRAM_SDTR2_XSNR_16_CLK		0x00100000
-#define SDRAM_SDTR2_XSNR_32_CLK		0x00200000
-#define SDRAM_SDTR2_XSNR_64_CLK		0x00400000
-#define SDRAM_SDTR2_WPC_MASK		0x0000F000
-#define SDRAM_SDTR2_WPC_2_CLK		0x00002000
-#define SDRAM_SDTR2_WPC_3_CLK		0x00003000
-#define SDRAM_SDTR2_WPC_4_CLK		0x00004000
-#define SDRAM_SDTR2_WPC_5_CLK		0x00005000
-#define SDRAM_SDTR2_WPC_6_CLK		0x00006000
-#define SDRAM_SDTR3_WPC_ENCODE(n)	((((u32)(n))&0xF)<<12)
-#define SDRAM_SDTR2_RPC_MASK		0x00000F00
-#define SDRAM_SDTR2_RPC_2_CLK		0x00000200
-#define SDRAM_SDTR2_RPC_3_CLK		0x00000300
-#define SDRAM_SDTR2_RPC_4_CLK		0x00000400
-#define SDRAM_SDTR2_RP_MASK		0x000000F0
-#define SDRAM_SDTR2_RP_3_CLK		0x00000030
-#define SDRAM_SDTR2_RP_4_CLK		0x00000040
-#define SDRAM_SDTR2_RP_5_CLK		0x00000050
-#define SDRAM_SDTR2_RP_6_CLK		0x00000060
-#define SDRAM_SDTR2_RP_7_CLK		0x00000070
-#define SDRAM_SDTR2_RRD_MASK		0x0000000F
-#define SDRAM_SDTR2_RRD_2_CLK		0x00000002
-#define SDRAM_SDTR2_RRD_3_CLK		0x00000003
-
-/*
- * SDRAM SDTR3 Options
- */
-#define SDRAM_SDTR3_RAS_MASK		0x1F000000
-#define SDRAM_SDTR3_RAS_ENCODE(n)	((((u32)(n))&0x1F)<<24)
-#define SDRAM_SDTR3_RC_MASK		0x001F0000
-#define SDRAM_SDTR3_RC_ENCODE(n)	((((u32)(n))&0x1F)<<16)
-#define SDRAM_SDTR3_XCS_MASK		0x00001F00
-#define SDRAM_SDTR3_XCS			0x00000D00
-#define SDRAM_SDTR3_RFC_MASK		0x0000003F
-#define SDRAM_SDTR3_RFC_ENCODE(n)	((((u32)(n))&0x3F)<<0)
-
-/*
- * ECC Error Status
- */
-#define SDRAM_ECCES_MASK		 PPC_REG_VAL(21, 0x3FFFFF)
-#define SDRAM_ECCES_BNCE_MASK		 PPC_REG_VAL(15, 0xFFFF)
-#define SDRAM_ECCES_BNCE_ENCODE(lane)	 PPC_REG_VAL(((lane) & 0xF), 1)
-#define SDRAM_ECCES_CKBER_MASK		 PPC_REG_VAL(17, 0x3)
-#define SDRAM_ECCES_CKBER_NONE		 PPC_REG_VAL(17, 0)
-#define SDRAM_ECCES_CKBER_16_ECC_0_3	 PPC_REG_VAL(17, 2)
-#define SDRAM_ECCES_CKBER_32_ECC_0_3	 PPC_REG_VAL(17, 1)
-#define SDRAM_ECCES_CKBER_32_ECC_4_8	 PPC_REG_VAL(17, 2)
-#define SDRAM_ECCES_CKBER_32_ECC_0_8	 PPC_REG_VAL(17, 3)
-#define SDRAM_ECCES_CE			 PPC_REG_VAL(18, 1)
-#define SDRAM_ECCES_UE			 PPC_REG_VAL(19, 1)
-#define SDRAM_ECCES_BKNER_MASK		 PPC_REG_VAL(21, 0x3)
-#define SDRAM_ECCES_BK0ER		 PPC_REG_VAL(20, 1)
-#define SDRAM_ECCES_BK1ER		 PPC_REG_VAL(21, 1)
-
-/*
- * Memory Bank 0-1 configuration
- */
-#define SDRAM_BXCF_M_AM_MASK		0x00000F00	/* Addressing mode	*/
-#define SDRAM_BXCF_M_AM_0		0x00000000	/*   Mode 0		*/
-#define SDRAM_BXCF_M_AM_1		0x00000100	/*   Mode 1		*/
-#define SDRAM_BXCF_M_AM_2		0x00000200	/*   Mode 2		*/
-#define SDRAM_BXCF_M_AM_3		0x00000300	/*   Mode 3		*/
-#define SDRAM_BXCF_M_AM_4		0x00000400	/*   Mode 4		*/
-#define SDRAM_BXCF_M_AM_5		0x00000500	/*   Mode 5		*/
-#define SDRAM_BXCF_M_AM_6		0x00000600	/*   Mode 6		*/
-#define SDRAM_BXCF_M_AM_7		0x00000700	/*   Mode 7		*/
-#define SDRAM_BXCF_M_AM_8		0x00000800	/*   Mode 8		*/
-#define SDRAM_BXCF_M_AM_9		0x00000900	/*   Mode 9		*/
-#define SDRAM_BXCF_M_BE_MASK		0x00000001	/* Memory Bank Enable	*/
-#define SDRAM_BXCF_M_BE_DISABLE		0x00000000	/* Memory Bank Enable	*/
-#define SDRAM_BXCF_M_BE_ENABLE		0x00000001	/* Memory Bank Enable	*/
-
-#define SDRAM_RTSR_TRK1SM_MASK		0xC0000000	/* Tracking State Mach 1*/
-#define SDRAM_RTSR_TRK1SM_ATBASE	0x00000000	/* atbase state		*/
-#define SDRAM_RTSR_TRK1SM_MISSED	0x40000000	/* missed state		*/
-#define SDRAM_RTSR_TRK1SM_ATPLS1	0x80000000	/* atpls1 state		*/
-#define SDRAM_RTSR_TRK1SM_RESET		0xC0000000	/* reset  state		*/
-
-#endif /* CONFIG_SDRAM_PPC4xx_IBM_DDR2 */
-
-#if defined(CONFIG_SDRAM_PPC4xx_DENALI_DDR2)
-/*
- * SDRAM Controller
- */
-#define DDR0_00				0x00
-#define DDR0_00_INT_ACK_MASK		0x7F000000	/* Write only */
-#define DDR0_00_INT_ACK_ALL		0x7F000000
-#define DDR0_00_INT_ACK_ENCODE(n)	((((u32)(n))&0x7F)<<24)
-#define DDR0_00_INT_ACK_DECODE(n)	((((u32)(n))>>24)&0x7F)
-/* Status */
-#define DDR0_00_INT_STATUS_MASK		0x00FF0000	/* Read only */
-/* Bit0. A single access outside the defined PHYSICAL memory space detected. */
-#define DDR0_00_INT_STATUS_BIT0		0x00010000
-/* Bit1. Multiple accesses outside the defined PHYSICAL memory space detected. */
-#define DDR0_00_INT_STATUS_BIT1		0x00020000
-/* Bit2. Single correctable ECC event detected */
-#define DDR0_00_INT_STATUS_BIT2		0x00040000
-/* Bit3. Multiple correctable ECC events detected. */
-#define DDR0_00_INT_STATUS_BIT3		0x00080000
-/* Bit4. Single uncorrectable ECC event detected. */
-#define DDR0_00_INT_STATUS_BIT4		0x00100000
-/* Bit5. Multiple uncorrectable ECC events detected. */
-#define DDR0_00_INT_STATUS_BIT5		0x00200000
-/* Bit6. DRAM initialization complete. */
-#define DDR0_00_INT_STATUS_BIT6		0x00400000
-/* Bit7. Logical OR of all lower bits. */
-#define DDR0_00_INT_STATUS_BIT7		0x00800000
-
-#define DDR0_00_INT_STATUS_ENCODE(n)	((((u32)(n))&0xFF)<<16)
-#define DDR0_00_INT_STATUS_DECODE(n)	((((u32)(n))>>16)&0xFF)
-#define DDR0_00_DLL_INCREMENT_MASK	0x00007F00
-#define DDR0_00_DLL_INCREMENT_ENCODE(n)	((((u32)(n))&0x7F)<<8)
-#define DDR0_00_DLL_INCREMENT_DECODE(n)	((((u32)(n))>>8)&0x7F)
-#define DDR0_00_DLL_START_POINT_MASK	0x0000007F
-#define DDR0_00_DLL_START_POINT_ENCODE(n) ((((u32)(n))&0x7F)<<0)
-#define DDR0_00_DLL_START_POINT_DECODE(n) ((((u32)(n))>>0)&0x7F)
-
-#define DDR0_01				0x01
-#define DDR0_01_PLB0_DB_CS_LOWER_MASK	0x1F000000
-#define DDR0_01_PLB0_DB_CS_LOWER_ENCODE(n) ((((u32)(n))&0x1F)<<24)
-#define DDR0_01_PLB0_DB_CS_LOWER_DECODE(n) ((((u32)(n))>>24)&0x1F)
-#define DDR0_01_PLB0_DB_CS_UPPER_MASK	0x001F0000
-#define DDR0_01_PLB0_DB_CS_UPPER_ENCODE(n) ((((u32)(n))&0x1F)<<16)
-#define DDR0_01_PLB0_DB_CS_UPPER_DECODE(n) ((((u32)(n))>>16)&0x1F)
-#define DDR0_01_OUT_OF_RANGE_TYPE_MASK	0x00000700	/* Read only */
-#define DDR0_01_OUT_OF_RANGE_TYPE_ENCODE(n) ((((u32)(n))&0x7)<<8)
-#define DDR0_01_OUT_OF_RANGE_TYPE_DECODE(n) ((((u32)(n))>>8)&0x7)
-#define DDR0_01_INT_MASK_MASK		0x000000FF
-#define DDR0_01_INT_MASK_ENCODE(n)	((((u32)(n))&0xFF)<<0)
-#define DDR0_01_INT_MASK_DECODE(n)	((((u32)(n))>>0)&0xFF)
-#define DDR0_01_INT_MASK_ALL_ON		0x000000FF
-#define DDR0_01_INT_MASK_ALL_OFF	0x00000000
-
-#define DDR0_02				0x02
-#define DDR0_02_MAX_CS_REG_MASK		0x02000000	/* Read only */
-#define DDR0_02_MAX_CS_REG_ENCODE(n)	((((u32)(n))&0x2)<<24)
-#define DDR0_02_MAX_CS_REG_DECODE(n)	((((u32)(n))>>24)&0x2)
-#define DDR0_02_MAX_COL_REG_MASK	0x000F0000	/* Read only */
-#define DDR0_02_MAX_COL_REG_ENCODE(n)	((((u32)(n))&0xF)<<16)
-#define DDR0_02_MAX_COL_REG_DECODE(n)	((((u32)(n))>>16)&0xF)
-#define DDR0_02_MAX_ROW_REG_MASK	0x00000F00	/* Read only */
-#define DDR0_02_MAX_ROW_REG_ENCODE(n)	((((u32)(n))&0xF)<<8)
-#define DDR0_02_MAX_ROW_REG_DECODE(n)	((((u32)(n))>>8)&0xF)
-#define DDR0_02_START_MASK		0x00000001
-#define DDR0_02_START_ENCODE(n)		((((u32)(n))&0x1)<<0)
-#define DDR0_02_START_DECODE(n)		((((u32)(n))>>0)&0x1)
-#define DDR0_02_START_OFF		0x00000000
-#define DDR0_02_START_ON		0x00000001
-
-#define DDR0_03				0x03
-#define DDR0_03_BSTLEN_MASK		0x07000000
-#define DDR0_03_BSTLEN_ENCODE(n)	((((u32)(n))&0x7)<<24)
-#define DDR0_03_BSTLEN_DECODE(n)	((((u32)(n))>>24)&0x7)
-#define DDR0_03_CASLAT_MASK		0x00070000
-#define DDR0_03_CASLAT_ENCODE(n)	((((u32)(n))&0x7)<<16)
-#define DDR0_03_CASLAT_DECODE(n)	((((u32)(n))>>16)&0x7)
-#define DDR0_03_CASLAT_LIN_MASK		0x00000F00
-#define DDR0_03_CASLAT_LIN_ENCODE(n)	((((u32)(n))&0xF)<<8)
-#define DDR0_03_CASLAT_LIN_DECODE(n)	((((u32)(n))>>8)&0xF)
-#define DDR0_03_INITAREF_MASK		0x0000000F
-#define DDR0_03_INITAREF_ENCODE(n)	((((u32)(n))&0xF)<<0)
-#define DDR0_03_INITAREF_DECODE(n)	((((u32)(n))>>0)&0xF)
-
-#define DDR0_04				0x04
-#define DDR0_04_TRC_MASK		0x1F000000
-#define DDR0_04_TRC_ENCODE(n)		((((u32)(n))&0x1F)<<24)
-#define DDR0_04_TRC_DECODE(n)		((((u32)(n))>>24)&0x1F)
-#define DDR0_04_TRRD_MASK		0x00070000
-#define DDR0_04_TRRD_ENCODE(n)		((((u32)(n))&0x7)<<16)
-#define DDR0_04_TRRD_DECODE(n)		((((u32)(n))>>16)&0x7)
-#define DDR0_04_TRTP_MASK		0x00000700
-#define DDR0_04_TRTP_ENCODE(n)		((((u32)(n))&0x7)<<8)
-#define DDR0_04_TRTP_DECODE(n)		((((u32)(n))>>8)&0x7)
-
-#define DDR0_05				0x05
-#define DDR0_05_TMRD_MASK		0x1F000000
-#define DDR0_05_TMRD_ENCODE(n)		((((u32)(n))&0x1F)<<24)
-#define DDR0_05_TMRD_DECODE(n)		((((u32)(n))>>24)&0x1F)
-#define DDR0_05_TEMRS_MASK		0x00070000
-#define DDR0_05_TEMRS_ENCODE(n)		((((u32)(n))&0x7)<<16)
-#define DDR0_05_TEMRS_DECODE(n)		((((u32)(n))>>16)&0x7)
-#define DDR0_05_TRP_MASK		0x00000F00
-#define DDR0_05_TRP_ENCODE(n)		((((u32)(n))&0xF)<<8)
-#define DDR0_05_TRP_DECODE(n)		((((u32)(n))>>8)&0xF)
-#define DDR0_05_TRAS_MIN_MASK		0x000000FF
-#define DDR0_05_TRAS_MIN_ENCODE(n)	((((u32)(n))&0xFF)<<0)
-#define DDR0_05_TRAS_MIN_DECODE(n)	((((u32)(n))>>0)&0xFF)
-
-#define DDR0_06				0x06
-#define DDR0_06_WRITEINTERP_MASK	0x01000000
-#define DDR0_06_WRITEINTERP_ENCODE(n)	((((u32)(n))&0x1)<<24)
-#define DDR0_06_WRITEINTERP_DECODE(n)	((((u32)(n))>>24)&0x1)
-#define DDR0_06_TWTR_MASK		0x00070000
-#define DDR0_06_TWTR_ENCODE(n)		((((u32)(n))&0x7)<<16)
-#define DDR0_06_TWTR_DECODE(n)		((((u32)(n))>>16)&0x7)
-#define DDR0_06_TDLL_MASK		0x0000FF00
-#define DDR0_06_TDLL_ENCODE(n)		((((u32)(n))&0xFF)<<8)
-#define DDR0_06_TDLL_DECODE(n)		((((u32)(n))>>8)&0xFF)
-#define DDR0_06_TRFC_MASK		0x0000007F
-#define DDR0_06_TRFC_ENCODE(n)		((((u32)(n))&0x7F)<<0)
-#define DDR0_06_TRFC_DECODE(n)		((((u32)(n))>>0)&0x7F)
-
-#define DDR0_07				0x07
-#define DDR0_07_NO_CMD_INIT_MASK	0x01000000
-#define DDR0_07_NO_CMD_INIT_ENCODE(n)	((((u32)(n))&0x1)<<24)
-#define DDR0_07_NO_CMD_INIT_DECODE(n)	((((u32)(n))>>24)&0x1)
-#define DDR0_07_TFAW_MASK		0x001F0000
-#define DDR0_07_TFAW_ENCODE(n)		((((u32)(n))&0x1F)<<16)
-#define DDR0_07_TFAW_DECODE(n)		((((u32)(n))>>16)&0x1F)
-#define DDR0_07_AUTO_REFRESH_MODE_MASK	0x00000100
-#define DDR0_07_AUTO_REFRESH_MODE_ENCODE(n) ((((u32)(n))&0x1)<<8)
-#define DDR0_07_AUTO_REFRESH_MODE_DECODE(n) ((((u32)(n))>>8)&0x1)
-#define DDR0_07_AREFRESH_MASK		0x00000001
-#define DDR0_07_AREFRESH_ENCODE(n)	((((u32)(n))&0x1)<<0)
-#define DDR0_07_AREFRESH_DECODE(n)	((((u32)(n))>>0)&0x1)
-
-#define DDR0_08				0x08
-#define DDR0_08_WRLAT_MASK		0x07000000
-#define DDR0_08_WRLAT_ENCODE(n)		((((u32)(n))&0x7)<<24)
-#define DDR0_08_WRLAT_DECODE(n)		((((u32)(n))>>24)&0x7)
-#define DDR0_08_TCPD_MASK		0x00FF0000
-#define DDR0_08_TCPD_ENCODE(n)		((((u32)(n))&0xFF)<<16)
-#define DDR0_08_TCPD_DECODE(n)		((((u32)(n))>>16)&0xFF)
-#define DDR0_08_DQS_N_EN_MASK		0x00000100
-#define DDR0_08_DQS_N_EN_ENCODE(n)	((((u32)(n))&0x1)<<8)
-#define DDR0_08_DQS_N_EN_DECODE(n)	((((u32)(n))>>8)&0x1)
-#define DDR0_08_DDRII_SDRAM_MODE_MASK	0x00000001
-#define DDR0_08_DDRII_ENCODE(n)		((((u32)(n))&0x1)<<0)
-#define DDR0_08_DDRII_DECODE(n)		((((u32)(n))>>0)&0x1)
-
-#define DDR0_09				0x09
-#define DDR0_09_OCD_ADJUST_PDN_CS_0_MASK 0x1F000000
-#define DDR0_09_OCD_ADJUST_PDN_CS_0_ENCODE(n) ((((u32)(n))&0x1F)<<24)
-#define DDR0_09_OCD_ADJUST_PDN_CS_0_DECODE(n) ((((u32)(n))>>24)&0x1F)
-#define DDR0_09_RTT_0_MASK		0x00030000
-#define DDR0_09_RTT_0_ENCODE(n)		((((u32)(n))&0x3)<<16)
-#define DDR0_09_RTT_0_DECODE(n)		((((u32)(n))>>16)&0x3)
-#define DDR0_09_WR_DQS_SHIFT_BYPASS_MASK  0x00007F00
-#define DDR0_09_WR_DQS_SHIFT_BYPASS_ENCODE(n) ((((u32)(n))&0x7F)<<8)
-#define DDR0_09_WR_DQS_SHIFT_BYPASS_DECODE(n) ((((u32)(n))>>8)&0x7F)
-#define DDR0_09_WR_DQS_SHIFT_MASK	0x0000007F
-#define DDR0_09_WR_DQS_SHIFT_ENCODE(n)	((((u32)(n))&0x7F)<<0)
-#define DDR0_09_WR_DQS_SHIFT_DECODE(n)	((((u32)(n))>>0)&0x7F)
-
-#define DDR0_10				0x0A
-#define DDR0_10_WRITE_MODEREG_MASK	0x00010000	/* Write only */
-#define DDR0_10_WRITE_MODEREG_ENCODE(n)	((((u32)(n))&0x1)<<16)
-#define DDR0_10_WRITE_MODEREG_DECODE(n)	((((u32)(n))>>16)&0x1)
-#define DDR0_10_CS_MAP_MASK		0x00000300
-#define DDR0_10_CS_MAP_NO_MEM		0x00000000
-#define DDR0_10_CS_MAP_RANK0_INSTALLED	0x00000100
-#define DDR0_10_CS_MAP_RANK1_INSTALLED	0x00000200
-#define DDR0_10_CS_MAP_ENCODE(n)	((((u32)(n))&0x3)<<8)
-#define DDR0_10_CS_MAP_DECODE(n)	((((u32)(n))>>8)&0x3)
-#define DDR0_10_OCD_ADJUST_PUP_CS_0_MASK  0x0000001F
-#define DDR0_10_OCD_ADJUST_PUP_CS_0_ENCODE(n) ((((u32)(n))&0x1F)<<0)
-#define DDR0_10_OCD_ADJUST_PUP_CS_0_DECODE(n) ((((u32)(n))>>0)&0x1F)
-
-#define DDR0_11				0x0B
-#define DDR0_11_SREFRESH_MASK		0x01000000
-#define DDR0_11_SREFRESH_ENCODE(n)	((((u32)(n))&0x1)<<24)
-#define DDR0_11_SREFRESH_DECODE(n)	((((u32)(n))>>24)&0x1F)
-#define DDR0_11_TXSNR_MASK		0x00FF0000
-#define DDR0_11_TXSNR_ENCODE(n)		((((u32)(n))&0xFF)<<16)
-#define DDR0_11_TXSNR_DECODE(n)		((((u32)(n))>>16)&0xFF)
-#define DDR0_11_TXSR_MASK		0x0000FF00
-#define DDR0_11_TXSR_ENCODE(n)		((((u32)(n))&0xFF)<<8)
-#define DDR0_11_TXSR_DECODE(n)		((((u32)(n))>>8)&0xFF)
-
-#define DDR0_12				0x0C
-#define DDR0_12_TCKE_MASK		0x0000007
-#define DDR0_12_TCKE_ENCODE(n)		((((u32)(n))&0x7)<<0)
-#define DDR0_12_TCKE_DECODE(n)		((((u32)(n))>>0)&0x7)
-
-#define DDR0_14				0x0E
-#define DDR0_14_DLL_BYPASS_MODE_MASK	0x01000000
-#define DDR0_14_DLL_BYPASS_MODE_ENCODE(n) ((((u32)(n))&0x1)<<24)
-#define DDR0_14_DLL_BYPASS_MODE_DECODE(n) ((((u32)(n))>>24)&0x1)
-#define DDR0_14_REDUC_MASK		0x00010000
-#define DDR0_14_REDUC_64BITS		0x00000000
-#define DDR0_14_REDUC_32BITS		0x00010000
-#define DDR0_14_REDUC_ENCODE(n)		((((u32)(n))&0x1)<<16)
-#define DDR0_14_REDUC_DECODE(n)		((((u32)(n))>>16)&0x1)
-#define DDR0_14_REG_DIMM_ENABLE_MASK	0x00000100
-#define DDR0_14_REG_DIMM_ENABLE_ENCODE(n) ((((u32)(n))&0x1)<<8)
-#define DDR0_14_REG_DIMM_ENABLE_DECODE(n) ((((u32)(n))>>8)&0x1)
-
-#define DDR0_17				0x11
-#define DDR0_17_DLL_DQS_DELAY_0_MASK	0x7F000000
-#define DDR0_17_DLL_DQS_DELAY_0_ENCODE(n) ((((u32)(n))&0x7F)<<24)
-#define DDR0_17_DLL_DQS_DELAY_0_DECODE(n) ((((u32)(n))>>24)&0x7F)
-#define DDR0_17_DLLLOCKREG_MASK		0x00010000	/* Read only */
-#define DDR0_17_DLLLOCKREG_LOCKED	0x00010000
-#define DDR0_17_DLLLOCKREG_UNLOCKED	0x00000000
-#define DDR0_17_DLLLOCKREG_ENCODE(n)	((((u32)(n))&0x1)<<16)
-#define DDR0_17_DLLLOCKREG_DECODE(n)	((((u32)(n))>>16)&0x1)
-#define DDR0_17_DLL_LOCK_MASK		0x00007F00	/* Read only */
-#define DDR0_17_DLL_LOCK_ENCODE(n)	((((u32)(n))&0x7F)<<8)
-#define DDR0_17_DLL_LOCK_DECODE(n)	((((u32)(n))>>8)&0x7F)
-
-#define DDR0_18				0x12
-#define DDR0_18_DLL_DQS_DELAY_X_MASK	0x7F7F7F7F
-#define DDR0_18_DLL_DQS_DELAY_4_MASK	0x7F000000
-#define DDR0_18_DLL_DQS_DELAY_4_ENCODE(n) ((((u32)(n))&0x7F)<<24)
-#define DDR0_18_DLL_DQS_DELAY_4_DECODE(n) ((((u32)(n))>>24)&0x7F)
-#define DDR0_18_DLL_DQS_DELAY_3_MASK	0x007F0000
-#define DDR0_18_DLL_DQS_DELAY_3_ENCODE(n) ((((u32)(n))&0x7F)<<16)
-#define DDR0_18_DLL_DQS_DELAY_3_DECODE(n) ((((u32)(n))>>16)&0x7F)
-#define DDR0_18_DLL_DQS_DELAY_2_MASK	0x00007F00
-#define DDR0_18_DLL_DQS_DELAY_2_ENCODE(n) ((((u32)(n))&0x7F)<<8)
-#define DDR0_18_DLL_DQS_DELAY_2_DECODE(n) ((((u32)(n))>>8)&0x7F)
-#define DDR0_18_DLL_DQS_DELAY_1_MASK	0x0000007F
-#define DDR0_18_DLL_DQS_DELAY_1_ENCODE(n) ((((u32)(n))&0x7F)<<0)
-#define DDR0_18_DLL_DQS_DELAY_1_DECODE(n) ((((u32)(n))>>0)&0x7F)
-
-#define DDR0_19				0x13
-#define DDR0_19_DLL_DQS_DELAY_X_MASK	0x7F7F7F7F
-#define DDR0_19_DLL_DQS_DELAY_8_MASK	0x7F000000
-#define DDR0_19_DLL_DQS_DELAY_8_ENCODE(n) ((((u32)(n))&0x7F)<<24)
-#define DDR0_19_DLL_DQS_DELAY_8_DECODE(n) ((((u32)(n))>>24)&0x7F)
-#define DDR0_19_DLL_DQS_DELAY_7_MASK	0x007F0000
-#define DDR0_19_DLL_DQS_DELAY_7_ENCODE(n) ((((u32)(n))&0x7F)<<16)
-#define DDR0_19_DLL_DQS_DELAY_7_DECODE(n) ((((u32)(n))>>16)&0x7F)
-#define DDR0_19_DLL_DQS_DELAY_6_MASK	0x00007F00
-#define DDR0_19_DLL_DQS_DELAY_6_ENCODE(n) ((((u32)(n))&0x7F)<<8)
-#define DDR0_19_DLL_DQS_DELAY_6_DECODE(n) ((((u32)(n))>>8)&0x7F)
-#define DDR0_19_DLL_DQS_DELAY_5_MASK	0x0000007F
-#define DDR0_19_DLL_DQS_DELAY_5_ENCODE(n) ((((u32)(n))&0x7F)<<0)
-#define DDR0_19_DLL_DQS_DELAY_5_DECODE(n) ((((u32)(n))>>0)&0x7F)
-
-#define DDR0_20				0x14
-#define DDR0_20_DLL_DQS_BYPASS_3_MASK	0x7F000000
-#define DDR0_20_DLL_DQS_BYPASS_3_ENCODE(n) ((((u32)(n))&0x7F)<<24)
-#define DDR0_20_DLL_DQS_BYPASS_3_DECODE(n) ((((u32)(n))>>24)&0x7F)
-#define DDR0_20_DLL_DQS_BYPASS_2_MASK	0x007F0000
-#define DDR0_20_DLL_DQS_BYPASS_2_ENCODE(n) ((((u32)(n))&0x7F)<<16)
-#define DDR0_20_DLL_DQS_BYPASS_2_DECODE(n) ((((u32)(n))>>16)&0x7F)
-#define DDR0_20_DLL_DQS_BYPASS_1_MASK	0x00007F00
-#define DDR0_20_DLL_DQS_BYPASS_1_ENCODE(n) ((((u32)(n))&0x7F)<<8)
-#define DDR0_20_DLL_DQS_BYPASS_1_DECODE(n) ((((u32)(n))>>8)&0x7F)
-#define DDR0_20_DLL_DQS_BYPASS_0_MASK	0x0000007F
-#define DDR0_20_DLL_DQS_BYPASS_0_ENCODE(n) ((((u32)(n))&0x7F)<<0)
-#define DDR0_20_DLL_DQS_BYPASS_0_DECODE(n) ((((u32)(n))>>0)&0x7F)
-
-#define DDR0_21				0x15
-#define DDR0_21_DLL_DQS_BYPASS_7_MASK	0x7F000000
-#define DDR0_21_DLL_DQS_BYPASS_7_ENCODE(n) ((((u32)(n))&0x7F)<<24)
-#define DDR0_21_DLL_DQS_BYPASS_7_DECODE(n) ((((u32)(n))>>24)&0x7F)
-#define DDR0_21_DLL_DQS_BYPASS_6_MASK	0x007F0000
-#define DDR0_21_DLL_DQS_BYPASS_6_ENCODE(n) ((((u32)(n))&0x7F)<<16)
-#define DDR0_21_DLL_DQS_BYPASS_6_DECODE(n) ((((u32)(n))>>16)&0x7F)
-#define DDR0_21_DLL_DQS_BYPASS_5_MASK	0x00007F00
-#define DDR0_21_DLL_DQS_BYPASS_5_ENCODE(n) ((((u32)(n))&0x7F)<<8)
-#define DDR0_21_DLL_DQS_BYPASS_5_DECODE(n) ((((u32)(n))>>8)&0x7F)
-#define DDR0_21_DLL_DQS_BYPASS_4_MASK	0x0000007F
-#define DDR0_21_DLL_DQS_BYPASS_4_ENCODE(n) ((((u32)(n))&0x7F)<<0)
-#define DDR0_21_DLL_DQS_BYPASS_4_DECODE(n) ((((u32)(n))>>0)&0x7F)
-
-#define DDR0_22				0x16
-#define DDR0_22_CTRL_RAW_MASK		0x03000000
-#define DDR0_22_CTRL_RAW_ECC_DISABLE	0x00000000
-#define DDR0_22_CTRL_RAW_ECC_CHECK_ONLY	0x01000000
-#define DDR0_22_CTRL_RAW_NO_ECC_RAM	0x02000000
-#define DDR0_22_CTRL_RAW_ECC_ENABLE	0x03000000
-#define DDR0_22_CTRL_RAW_ENCODE(n)	((((u32)(n))&0x3)<<24)
-#define DDR0_22_CTRL_RAW_DECODE(n)	((((u32)(n))>>24)&0x3)
-#define DDR0_22_DQS_OUT_SHIFT_BYPASS_MASK 0x007F0000
-#define DDR0_22_DQS_OUT_SHIFT_BYPASS_ENCODE(n) ((((u32)(n))&0x7F)<<16)
-#define DDR0_22_DQS_OUT_SHIFT_BYPASS_DECODE(n) ((((u32)(n))>>16)&0x7F)
-#define DDR0_22_DQS_OUT_SHIFT_MASK	0x00007F00
-#define DDR0_22_DQS_OUT_SHIFT_ENCODE(n)	((((u32)(n))&0x7F)<<8)
-#define DDR0_22_DQS_OUT_SHIFT_DECODE(n)	((((u32)(n))>>8)&0x7F)
-#define DDR0_22_DLL_DQS_BYPASS_8_MASK	0x0000007F
-#define DDR0_22_DLL_DQS_BYPASS_8_ENCODE(n) ((((u32)(n))&0x7F)<<0)
-#define DDR0_22_DLL_DQS_BYPASS_8_DECODE(n) ((((u32)(n))>>0)&0x7F)
-
-#define DDR0_23				0x17
-#define DDR0_23_ODT_RD_MAP_CS0_MASK	0x03000000
-#define DDR0_23_ODT_RD_MAP_CS0_ENCODE(n) ((((u32)(n))&0x3)<<24)
-#define DDR0_23_ODT_RD_MAP_CS0_DECODE(n) ((((u32)(n))>>24)&0x3)
-#define DDR0_23_ECC_C_SYND_MASK		0x00FF0000	/* Read only */
-#define DDR0_23_ECC_C_SYND_ENCODE(n)	((((u32)(n))&0xFF)<<16)
-#define DDR0_23_ECC_C_SYND_DECODE(n)	((((u32)(n))>>16)&0xFF)
-#define DDR0_23_ECC_U_SYND_MASK		0x0000FF00	/* Read only */
-#define DDR0_23_ECC_U_SYND_ENCODE(n)	((((u32)(n))&0xFF)<<8)
-#define DDR0_23_ECC_U_SYND_DECODE(n)	((((u32)(n))>>8)&0xFF)
-#define DDR0_23_FWC_MASK		0x00000001	/* Write only */
-#define DDR0_23_FWC_ENCODE(n)		((((u32)(n))&0x1)<<0)
-#define DDR0_23_FWC_DECODE(n)		((((u32)(n))>>0)&0x1)
-
-#define DDR0_24				0x18
-#define DDR0_24_RTT_PAD_TERMINATION_MASK 0x03000000
-#define DDR0_24_RTT_PAD_TERMINATION_ENCODE(n) ((((u32)(n))&0x3)<<24)
-#define DDR0_24_RTT_PAD_TERMINATION_DECODE(n) ((((u32)(n))>>24)&0x3)
-#define DDR0_24_ODT_WR_MAP_CS1_MASK	0x00030000
-#define DDR0_24_ODT_WR_MAP_CS1_ENCODE(n) ((((u32)(n))&0x3)<<16)
-#define DDR0_24_ODT_WR_MAP_CS1_DECODE(n) ((((u32)(n))>>16)&0x3)
-#define DDR0_24_ODT_RD_MAP_CS1_MASK	0x00000300
-#define DDR0_24_ODT_RD_MAP_CS1_ENCODE(n) ((((u32)(n))&0x3)<<8)
-#define DDR0_24_ODT_RD_MAP_CS1_DECODE(n) ((((u32)(n))>>8)&0x3)
-#define DDR0_24_ODT_WR_MAP_CS0_MASK	0x00000003
-#define DDR0_24_ODT_WR_MAP_CS0_ENCODE(n) ((((u32)(n))&0x3)<<0)
-#define DDR0_24_ODT_WR_MAP_CS0_DECODE(n) ((((u32)(n))>>0)&0x3)
-
-#define DDR0_25				0x19
-#define DDR0_25_VERSION_MASK		0xFFFF0000	/* Read only */
-#define DDR0_25_VERSION_ENCODE(n)	((((u32)(n))&0xFFFF)<<16)
-#define DDR0_25_VERSION_DECODE(n)	((((u32)(n))>>16)&0xFFFF)
-#define DDR0_25_OUT_OF_RANGE_LENGTH_MASK  0x000003FF	/* Read only */
-#define DDR0_25_OUT_OF_RANGE_LENGTH_ENCODE(n) ((((u32)(n))&0x3FF)<<0)
-#define DDR0_25_OUT_OF_RANGE_LENGTH_DECODE(n) ((((u32)(n))>>0)&0x3FF)
-
-#define DDR0_26				0x1A
-#define DDR0_26_TRAS_MAX_MASK		0xFFFF0000
-#define DDR0_26_TRAS_MAX_ENCODE(n)	((((u32)(n))&0xFFFF)<<16)
-#define DDR0_26_TRAS_MAX_DECODE(n)	((((u32)(n))>>16)&0xFFFF)
-#define DDR0_26_TREF_MASK		0x00003FFF
-#define DDR0_26_TREF_ENCODE(n)		((((u32)(n))&0x3FFF)<<0)
-#define DDR0_26_TREF_DECODE(n)		((((u32)(n))>>0)&0x3FFF)
-
-#define DDR0_27				0x1B
-#define DDR0_27_EMRS_DATA_MASK		0x3FFF0000
-#define DDR0_27_EMRS_DATA_ENCODE(n)	((((u32)(n))&0x3FFF)<<16)
-#define DDR0_27_EMRS_DATA_DECODE(n)	((((u32)(n))>>16)&0x3FFF)
-#define DDR0_27_TINIT_MASK		0x0000FFFF
-#define DDR0_27_TINIT_ENCODE(n)		((((u32)(n))&0xFFFF)<<0)
-#define DDR0_27_TINIT_DECODE(n)		((((u32)(n))>>0)&0xFFFF)
-
-#define DDR0_28				0x1C
-#define DDR0_28_EMRS3_DATA_MASK		0x3FFF0000
-#define DDR0_28_EMRS3_DATA_ENCODE(n)	((((u32)(n))&0x3FFF)<<16)
-#define DDR0_28_EMRS3_DATA_DECODE(n)	((((u32)(n))>>16)&0x3FFF)
-#define DDR0_28_EMRS2_DATA_MASK		0x00003FFF
-#define DDR0_28_EMRS2_DATA_ENCODE(n)	((((u32)(n))&0x3FFF)<<0)
-#define DDR0_28_EMRS2_DATA_DECODE(n)	((((u32)(n))>>0)&0x3FFF)
-
-#define DDR0_31				0x1F
-#define DDR0_31_XOR_CHECK_BITS_MASK	0x0000FFFF
-#define DDR0_31_XOR_CHECK_BITS_ENCODE(n) ((((u32)(n))&0xFFFF)<<0)
-#define DDR0_31_XOR_CHECK_BITS_DECODE(n) ((((u32)(n))>>0)&0xFFFF)
-
-#define DDR0_32				0x20
-#define DDR0_32_OUT_OF_RANGE_ADDR_MASK	0xFFFFFFFF	/* Read only */
-#define DDR0_32_OUT_OF_RANGE_ADDR_ENCODE(n) ((((u32)(n))&0xFFFFFFFF)<<0)
-#define DDR0_32_OUT_OF_RANGE_ADDR_DECODE(n) ((((u32)(n))>>0)&0xFFFFFFFF)
-
-#define DDR0_33				0x21
-#define DDR0_33_OUT_OF_RANGE_ADDR_MASK	0x00000001	/* Read only */
-#define DDR0_33_OUT_OF_RANGE_ADDR_ENCODE(n) ((((u32)(n))&0x1)<<0)
-#define DDR0_33_OUT_OF_RANGE_ADDR_DECODE(n) ((((u32)(n))>>0)&0x1)
-
-#define DDR0_34				0x22
-#define DDR0_34_ECC_U_ADDR_MASK		0xFFFFFFFF	/* Read only */
-#define DDR0_34_ECC_U_ADDR_ENCODE(n)	((((u32)(n))&0xFFFFFFFF)<<0)
-#define DDR0_34_ECC_U_ADDR_DECODE(n)	((((u32)(n))>>0)&0xFFFFFFFF)
-
-#define DDR0_35				0x23
-#define DDR0_35_ECC_U_ADDR_MASK		0x00000001	/* Read only */
-#define DDR0_35_ECC_U_ADDR_ENCODE(n)	((((u32)(n))&0x1)<<0)
-#define DDR0_35_ECC_U_ADDR_DECODE(n)	((((u32)(n))>>0)&0x1)
-
-#define DDR0_36				0x24
-#define DDR0_36_ECC_U_DATA_MASK		0xFFFFFFFF	/* Read only */
-#define DDR0_36_ECC_U_DATA_ENCODE(n)	((((u32)(n))&0xFFFFFFFF)<<0)
-#define DDR0_36_ECC_U_DATA_DECODE(n)	((((u32)(n))>>0)&0xFFFFFFFF)
-
-#define DDR0_37				0x25
-#define DDR0_37_ECC_U_DATA_MASK		0xFFFFFFFF	/* Read only */
-#define DDR0_37_ECC_U_DATA_ENCODE(n)	((((u32)(n))&0xFFFFFFFF)<<0)
-#define DDR0_37_ECC_U_DATA_DECODE(n)	((((u32)(n))>>0)&0xFFFFFFFF)
-
-#define DDR0_38				0x26
-#define DDR0_38_ECC_C_ADDR_MASK		0xFFFFFFFF	/* Read only */
-#define DDR0_38_ECC_C_ADDR_ENCODE(n)	((((u32)(n))&0xFFFFFFFF)<<0)
-#define DDR0_38_ECC_C_ADDR_DECODE(n)	((((u32)(n))>>0)&0xFFFFFFFF)
-
-#define DDR0_39				0x27
-#define DDR0_39_ECC_C_ADDR_MASK		0x00000001	/* Read only */
-#define DDR0_39_ECC_C_ADDR_ENCODE(n)	((((u32)(n))&0x1)<<0)
-#define DDR0_39_ECC_C_ADDR_DECODE(n)	((((u32)(n))>>0)&0x1)
-
-#define DDR0_40				0x28
-#define DDR0_40_ECC_C_DATA_MASK		0xFFFFFFFF	/* Read only */
-#define DDR0_40_ECC_C_DATA_ENCODE(n)	((((u32)(n))&0xFFFFFFFF)<<0)
-#define DDR0_40_ECC_C_DATA_DECODE(n)	((((u32)(n))>>0)&0xFFFFFFFF)
-
-#define DDR0_41				0x29
-#define DDR0_41_ECC_C_DATA_MASK		0xFFFFFFFF	/* Read only */
-#define DDR0_41_ECC_C_DATA_ENCODE(n)	((((u32)(n))&0xFFFFFFFF)<<0)
-#define DDR0_41_ECC_C_DATA_DECODE(n)	((((u32)(n))>>0)&0xFFFFFFFF)
-
-#define DDR0_42				0x2A
-#define DDR0_42_ADDR_PINS_MASK		0x07000000
-#define DDR0_42_ADDR_PINS_ENCODE(n)	((((u32)(n))&0x7)<<24)
-#define DDR0_42_ADDR_PINS_DECODE(n)	((((u32)(n))>>24)&0x7)
-#define DDR0_42_CASLAT_LIN_GATE_MASK	0x0000000F
-#define DDR0_42_CASLAT_LIN_GATE_ENCODE(n) ((((u32)(n))&0xF)<<0)
-#define DDR0_42_CASLAT_LIN_GATE_DECODE(n) ((((u32)(n))>>0)&0xF)
-
-#define DDR0_43				0x2B
-#define DDR0_43_TWR_MASK		0x07000000
-#define DDR0_43_TWR_ENCODE(n)		((((u32)(n))&0x7)<<24)
-#define DDR0_43_TWR_DECODE(n)		((((u32)(n))>>24)&0x7)
-#define DDR0_43_APREBIT_MASK		0x000F0000
-#define DDR0_43_APREBIT_ENCODE(n)	((((u32)(n))&0xF)<<16)
-#define DDR0_43_APREBIT_DECODE(n)	((((u32)(n))>>16)&0xF)
-#define DDR0_43_COLUMN_SIZE_MASK	0x00000700
-#define DDR0_43_COLUMN_SIZE_ENCODE(n)	((((u32)(n))&0x7)<<8)
-#define DDR0_43_COLUMN_SIZE_DECODE(n)	((((u32)(n))>>8)&0x7)
-#define DDR0_43_EIGHT_BANK_MODE_MASK	0x00000001
-#define DDR0_43_EIGHT_BANK_MODE_8_BANKS	0x00000001
-#define DDR0_43_EIGHT_BANK_MODE_4_BANKS	0x00000000
-#define DDR0_43_EIGHT_BANK_MODE_ENCODE(n) ((((u32)(n))&0x1)<<0)
-#define DDR0_43_EIGHT_BANK_MODE_DECODE(n) ((((u32)(n))>>0)&0x1)
-
-#define DDR0_44				0x2C
-#define DDR0_44_TRCD_MASK		0x000000FF
-#define DDR0_44_TRCD_ENCODE(n)		((((u32)(n))&0xFF)<<0)
-#define DDR0_44_TRCD_DECODE(n)		((((u32)(n))>>0)&0xFF)
-
-#endif /* CONFIG_SDRAM_PPC4xx_DENALI_DDR2 */
-
-#ifndef __ASSEMBLY__
-struct sdram_timing {
-	u32 wrdtr;
-	u32 clktr;
-};
-
-/*
- * Prototypes
- */
-void ppc4xx_ibm_ddr2_register_dump(void);
-u32 mfdcr_any(u32);
-void mtdcr_any(u32, u32);
-u32 ddr_wrdtr(u32);
-u32 ddr_clktr(u32);
-void spd_ddr_init_hang(void);
-u32 DQS_autocalibration(void);
-phys_size_t sdram_memsize(void);
-void dcbz_area(u32 start_address, u32 num_bytes);
-#endif /* __ASSEMBLY__ */
-
-#endif /* _PPC4xx_SDRAM_H_ */
diff --git a/arch/powerpc/include/asm/ppc4xx-uic.h b/arch/powerpc/include/asm/ppc4xx-uic.h
deleted file mode 100644
index 58e65c1..0000000
--- a/arch/powerpc/include/asm/ppc4xx-uic.h
+++ /dev/null
@@ -1,288 +0,0 @@
-/*
- *  Copyright (C) 2002 Scott McNutt <smcnutt@artesyncp.com>
- *
- * (C) Copyright 2008-2009
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef _PPC4xx_UIC_H_
-#define _PPC4xx_UIC_H_
-
-/*
- * Define the number of UIC's
- */
-#if defined(CONFIG_440GX) || defined(CONFIG_440SPE) || \
-    defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
-    defined(CONFIG_460SX)
-#define UIC_MAX		4
-#elif defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
-    defined(CONFIG_405EX)
-#define UIC_MAX		3
-#elif defined(CONFIG_440GP) || defined(CONFIG_440SP) || \
-    defined(CONFIG_440EP) || defined(CONFIG_440GR)
-#define UIC_MAX		2
-#else
-#define UIC_MAX		1
-#endif
-
-#define IRQ_MAX		(UIC_MAX * 32)
-
-/*
- * UIC register
- */
-#define UIC_SR	0x0			/* UIC status			*/
-#define UIC_ER	0x2			/* UIC enable			*/
-#define UIC_CR	0x3			/* UIC critical			*/
-#define UIC_PR	0x4			/* UIC polarity			*/
-#define UIC_TR	0x5			/* UIC triggering		*/
-#define UIC_MSR 0x6			/* UIC masked status		*/
-#define UIC_VR	0x7			/* UIC vector			*/
-#define UIC_VCR 0x8			/* UIC vector configuration	*/
-
-/*
- * On 440GX we use the UICB0 as UIC0. Its the root UIC where all other UIC's
- * are cascaded on. With this trick we can use the common UIC code for 440GX
- * too.
- */
-#if defined(CONFIG_440GX)
-#define UIC0_DCR_BASE 0x200
-#define UIC1_DCR_BASE 0xc0
-#define UIC2_DCR_BASE 0xd0
-#define UIC3_DCR_BASE 0x210
-#else
-#define UIC0_DCR_BASE 0xc0
-#define UIC1_DCR_BASE 0xd0
-#define UIC2_DCR_BASE 0xe0
-#define UIC3_DCR_BASE 0xf0
-#endif
-
-#define UIC0SR	(UIC0_DCR_BASE+0x0)	/* UIC0 status			*/
-#define UIC0ER	(UIC0_DCR_BASE+0x2)	/* UIC0 enable			*/
-#define UIC0CR	(UIC0_DCR_BASE+0x3)	/* UIC0 critical		*/
-#define UIC0PR	(UIC0_DCR_BASE+0x4)	/* UIC0 polarity		*/
-#define UIC0TR	(UIC0_DCR_BASE+0x5)	/* UIC0 triggering		*/
-#define UIC0MSR (UIC0_DCR_BASE+0x6)	/* UIC0 masked status		*/
-#define UIC0VR	(UIC0_DCR_BASE+0x7)	/* UIC0 vector			*/
-#define UIC0VCR (UIC0_DCR_BASE+0x8)	/* UIC0 vector configuration	*/
-
-#define UIC1SR	(UIC1_DCR_BASE+0x0)	/* UIC1 status			*/
-#define UIC1ER	(UIC1_DCR_BASE+0x2)	/* UIC1 enable			*/
-#define UIC1CR	(UIC1_DCR_BASE+0x3)	/* UIC1 critical		*/
-#define UIC1PR	(UIC1_DCR_BASE+0x4)	/* UIC1 polarity		*/
-#define UIC1TR	(UIC1_DCR_BASE+0x5)	/* UIC1 triggering		*/
-#define UIC1MSR (UIC1_DCR_BASE+0x6)	/* UIC1 masked status		*/
-#define UIC1VR	(UIC1_DCR_BASE+0x7)	/* UIC1 vector			*/
-#define UIC1VCR (UIC1_DCR_BASE+0x8)	/* UIC1 vector configuration	*/
-
-#define UIC2SR	(UIC2_DCR_BASE+0x0)	/* UIC2 status-Read Clear	*/
-#define UIC2ER	(UIC2_DCR_BASE+0x2)	/* UIC2 enable			*/
-#define UIC2CR	(UIC2_DCR_BASE+0x3)	/* UIC2 critical		*/
-#define UIC2PR	(UIC2_DCR_BASE+0x4)	/* UIC2 polarity		*/
-#define UIC2TR	(UIC2_DCR_BASE+0x5)	/* UIC2 triggering		*/
-#define UIC2MSR (UIC2_DCR_BASE+0x6)	/* UIC2 masked status		*/
-#define UIC2VR	(UIC2_DCR_BASE+0x7)	/* UIC2 vector			*/
-#define UIC2VCR (UIC2_DCR_BASE+0x8)	/* UIC2 vector configuration	*/
-
-#define UIC3SR	(UIC3_DCR_BASE+0x0)	/* UIC3 status-Read Clear	*/
-#define UIC3ER	(UIC3_DCR_BASE+0x2)	/* UIC3 enable			*/
-#define UIC3CR	(UIC3_DCR_BASE+0x3)	/* UIC3 critical		*/
-#define UIC3PR	(UIC3_DCR_BASE+0x4)	/* UIC3 polarity		*/
-#define UIC3TR	(UIC3_DCR_BASE+0x5)	/* UIC3 triggering		*/
-#define UIC3MSR (UIC3_DCR_BASE+0x6)	/* UIC3 masked status		*/
-#define UIC3VR	(UIC3_DCR_BASE+0x7)	/* UIC3 vector			*/
-#define UIC3VCR (UIC3_DCR_BASE+0x8)	/* UIC3 vector configuration	*/
-
-/*
- * Now the interrupt vector definitions. They are different for most of
- * the 4xx variants, so we need some more #ifdef's here. No mask
- * definitions anymore here. For this please use the UIC_MASK macro below.
- *
- * Note: Please only define the interrupts really used in U-Boot here.
- * Those are the cascading and EMAC/MAL related interrupt.
- */
-
-#if defined(CONFIG_405EP) || defined(CONFIG_405GP)
-#define VECNUM_MAL_SERR		10
-#define VECNUM_MAL_TXEOB	11
-#define VECNUM_MAL_RXEOB	12
-#define VECNUM_MAL_TXDE		13
-#define VECNUM_MAL_RXDE		14
-#define VECNUM_ETH0		15
-#define VECNUM_ETH1_OFFS	2
-#define VECNUM_EIRQ6		29
-#endif /* defined(CONFIG_405EP) */
-
-#if defined(CONFIG_405EZ)
-#define VECNUM_USBDEV		15
-#define VECNUM_ETH0		16
-#define VECNUM_MAL_SERR		18
-#define VECNUM_MAL_TXDE		18
-#define VECNUM_MAL_RXDE		18
-#define VECNUM_MAL_TXEOB	19
-#define VECNUM_MAL_RXEOB	21
-#endif /* CONFIG_405EX */
-
-#if defined(CONFIG_405EX)
-/* UIC 0 */
-#define VECNUM_MAL_TXEOB	10
-#define VECNUM_MAL_RXEOB	11
-#define VECNUM_ETH0		24
-#define VECNUM_ETH1_OFFS	1
-#define VECNUM_UIC2NCI		28
-#define VECNUM_UIC2CI		29
-#define VECNUM_UIC1NCI		30
-#define VECNUM_UIC1CI		31
-
-/* UIC 1 */
-#define VECNUM_MAL_SERR		(32 + 0)
-#define VECNUM_MAL_TXDE		(32 + 1)
-#define VECNUM_MAL_RXDE		(32 + 2)
-#endif /* CONFIG_405EX */
-
-#if defined(CONFIG_440GP) || \
-    defined(CONFIG_440EP) || defined(CONFIG_440GR)
-/* UIC 0 */
-#define VECNUM_MAL_TXEOB	10
-#define VECNUM_MAL_RXEOB	11
-#define VECNUM_UIC1NCI		30
-#define VECNUM_UIC1CI		31
-
-/* UIC 1 */
-#define VECNUM_MAL_SERR		(32 + 0)
-#define VECNUM_MAL_TXDE		(32 + 1)
-#define VECNUM_MAL_RXDE		(32 + 2)
-#define VECNUM_USBDEV		(32 + 23)
-#define VECNUM_ETH0		(32 + 28)
-#define VECNUM_ETH1_OFFS	2
-#endif /* CONFIG_440GP */
-
-#if defined(CONFIG_440GX)
-/* UICB 0 (440GX only) */
-/*
- * All those defines below are off-by-one, so that the common UIC code
- * can be used. So VECNUM_UIC1CI refers to VECNUM_UIC0CI etc.
- */
-#define VECNUM_UIC1CI		0
-#define VECNUM_UIC1NCI		1
-#define VECNUM_UIC2CI		2
-#define VECNUM_UIC2NCI		3
-#define VECNUM_UIC3CI		4
-#define VECNUM_UIC3NCI		5
-
-/* UIC 0, used as UIC1 on 440GX because of UICB0 */
-#define VECNUM_MAL_TXEOB	(32 + 10)
-#define VECNUM_MAL_RXEOB	(32 + 11)
-
-/* UIC 1, used as UIC2 on 440GX because of UICB0 */
-#define VECNUM_MAL_SERR		(64 + 0)
-#define VECNUM_MAL_TXDE		(64 + 1)
-#define VECNUM_MAL_RXDE		(64 + 2)
-#define VECNUM_ETH0		(64 + 28)
-#define VECNUM_ETH1_OFFS	2
-#endif /* CONFIG_440GX */
-
-#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
-/* UIC 0 */
-#define VECNUM_MAL_TXEOB	10
-#define VECNUM_MAL_RXEOB	11
-#define VECNUM_USBDEV		20
-#define VECNUM_ETH0		24
-#define VECNUM_ETH1_OFFS	1
-#define VECNUM_UIC2NCI		28
-#define VECNUM_UIC2CI		29
-#define VECNUM_UIC1NCI		30
-#define VECNUM_UIC1CI		31
-
-/* UIC 1 */
-#define VECNUM_MAL_SERR		(32 + 0)
-#define VECNUM_MAL_TXDE		(32 + 1)
-#define VECNUM_MAL_RXDE		(32 + 2)
-
-/* UIC 2 */
-#define VECNUM_EIRQ2		(64 + 3)
-#endif /* CONFIG_440EPX */
-
-#if defined(CONFIG_440SP)
-/* UIC 0 */
-#define VECNUM_UIC1NCI		30
-#define VECNUM_UIC1CI		31
-
-/* UIC 1 */
-#define VECNUM_MAL_SERR		(32 + 1)
-#define VECNUM_MAL_TXDE		(32 + 2)
-#define VECNUM_MAL_RXDE		(32 + 3)
-#define VECNUM_MAL_TXEOB	(32 + 6)
-#define VECNUM_MAL_RXEOB	(32 + 7)
-#define VECNUM_ETH0		(32 + 28)
-#endif /* CONFIG_440SP */
-
-#if defined(CONFIG_440SPE)
-/* UIC 0 */
-#define VECNUM_UIC2NCI		10
-#define VECNUM_UIC2CI		11
-#define VECNUM_UIC3NCI		16
-#define VECNUM_UIC3CI		17
-#define VECNUM_UIC1NCI		30
-#define VECNUM_UIC1CI		31
-
-/* UIC 1 */
-#define VECNUM_MAL_SERR		(32 + 1)
-#define VECNUM_MAL_TXDE		(32 + 2)
-#define VECNUM_MAL_RXDE		(32 + 3)
-#define VECNUM_MAL_TXEOB	(32 + 6)
-#define VECNUM_MAL_RXEOB	(32 + 7)
-#define VECNUM_ETH0		(32 + 28)
-#endif /* CONFIG_440SPE */
-
-#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
-/* UIC 0 */
-#define VECNUM_UIC2NCI		10
-#define VECNUM_UIC2CI		11
-#define VECNUM_UIC3NCI		16
-#define VECNUM_UIC3CI		17
-#define VECNUM_UIC1NCI		30
-#define VECNUM_UIC1CI		31
-
-/* UIC 2 */
-#define VECNUM_MAL_SERR		(64 + 3)
-#define	VECNUM_MAL_TXDE		(64 + 4)
-#define	VECNUM_MAL_RXDE		(64 + 5)
-#define VECNUM_MAL_TXEOB	(64 + 6)
-#define	VECNUM_MAL_RXEOB	(64 + 7)
-#define	VECNUM_ETH0		(64 + 16)
-#define VECNUM_ETH1_OFFS	1
-#endif /* CONFIG_460EX */
-
-#if defined(CONFIG_460SX)
-/* UIC 0 */
-#define VECNUM_UIC2NCI		10
-#define VECNUM_UIC2CI		11
-#define VECNUM_UIC3NCI		16
-#define VECNUM_UIC3CI		17
-#define	VECNUM_ETH0		19
-#define VECNUM_ETH1_OFFS	1
-#define VECNUM_UIC1NCI		30
-#define VECNUM_UIC1CI		31
-
-/* UIC 1 */
-#define VECNUM_MAL_SERR		(32 + 1)
-#define	VECNUM_MAL_TXDE		(32 + 2)
-#define	VECNUM_MAL_RXDE		(32 + 3)
-#define VECNUM_MAL_TXEOB	(32 + 6)
-#define	VECNUM_MAL_RXEOB	(32 + 7)
-#endif /* CONFIG_460EX */
-
-#if !defined(VECNUM_ETH1_OFFS)
-#define VECNUM_ETH1_OFFS	1
-#endif
-
-/*
- * Mask definitions (used for example in 4xx_enet.c)
- */
-#define UIC_MASK(vec)		(0x80000000 >> ((vec) & 0x1f))
-/* UIC_NR won't work for 440GX because of its specific UIC DCR addresses */
-#define UIC_NR(vec)		((vec) >> 5)
-
-#endif /* _PPC4xx_UIC_H_ */
diff --git a/arch/powerpc/include/asm/ppc4xx.h b/arch/powerpc/include/asm/ppc4xx.h
deleted file mode 100644
index 45ff5db..0000000
--- a/arch/powerpc/include/asm/ppc4xx.h
+++ /dev/null
@@ -1,304 +0,0 @@
-/*
- * SPDX-License-Identifier:	GPL-2.0	IBM-pibs
- */
-
-#ifndef	__PPC4XX_H__
-#define __PPC4XX_H__
-
-/*
- * Include SoC specific headers
- */
-#if defined(CONFIG_405EP)
-#include <asm/ppc405ep.h>
-#endif
-
-#if defined(CONFIG_405EX)
-#include <asm/ppc405ex.h>
-#endif
-
-#if defined(CONFIG_405EZ)
-#include <asm/ppc405ez.h>
-#endif
-
-#if defined(CONFIG_405GP)
-#include <asm/ppc405gp.h>
-#endif
-
-#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
-#include <asm/ppc440ep_gr.h>
-#endif
-
-#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
-#include <asm/ppc440epx_grx.h>
-#endif
-
-#if defined(CONFIG_440GP)
-#include <asm/ppc440gp.h>
-#endif
-
-#if defined(CONFIG_440GX)
-#include <asm/ppc440gx.h>
-#endif
-
-#if defined(CONFIG_440SP)
-#include <asm/ppc440sp.h>
-#endif
-
-#if defined(CONFIG_440SPE)
-#include <asm/ppc440spe.h>
-#endif
-
-#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
-#include <asm/ppc460ex_gt.h>
-#endif
-
-#if defined(CONFIG_460SX)
-#include <asm/ppc460sx.h>
-#endif
-
-/*
- * Common registers for all SoC's
- */
-/* DCR registers */
-#define PLB3A0_ACR	0x0077
-#define PLB4A0_ACR	0x0081
-#define PLB4A1_ACR	0x0089
-
-/* CPR register declarations */
-
-#define PLB4Ax_ACR_PPM_MASK		0xf0000000
-#define PLB4Ax_ACR_PPM_FIXED		0x00000000
-#define PLB4Ax_ACR_PPM_FAIR		0xd0000000
-#define PLB4Ax_ACR_HBU_MASK		0x08000000
-#define PLB4Ax_ACR_HBU_DISABLED		0x00000000
-#define PLB4Ax_ACR_HBU_ENABLED		0x08000000
-#define PLB4Ax_ACR_RDP_MASK		0x06000000
-#define PLB4Ax_ACR_RDP_DISABLED		0x00000000
-#define PLB4Ax_ACR_RDP_2DEEP		0x02000000
-#define PLB4Ax_ACR_RDP_3DEEP		0x04000000
-#define PLB4Ax_ACR_RDP_4DEEP		0x06000000
-#define PLB4Ax_ACR_WRP_MASK		0x01000000
-#define PLB4Ax_ACR_WRP_DISABLED		0x00000000
-#define PLB4Ax_ACR_WRP_2DEEP		0x01000000
-
-/*
- * External Bus Controller
- */
-/* Values for EBC0_CFGADDR register - indirect addressing of these regs */
-#define PB0CR		0x00	/* periph bank 0 config reg		*/
-#define PB1CR		0x01	/* periph bank 1 config reg		*/
-#define PB2CR		0x02	/* periph bank 2 config reg		*/
-#define PB3CR		0x03	/* periph bank 3 config reg		*/
-#define PB4CR		0x04	/* periph bank 4 config reg		*/
-#define PB5CR		0x05	/* periph bank 5 config reg		*/
-#define PB6CR		0x06	/* periph bank 6 config reg		*/
-#define PB7CR		0x07	/* periph bank 7 config reg		*/
-#define PB0AP		0x10	/* periph bank 0 access parameters	*/
-#define PB1AP		0x11	/* periph bank 1 access parameters	*/
-#define PB2AP		0x12	/* periph bank 2 access parameters	*/
-#define PB3AP		0x13	/* periph bank 3 access parameters	*/
-#define PB4AP		0x14	/* periph bank 4 access parameters	*/
-#define PB5AP		0x15	/* periph bank 5 access parameters	*/
-#define PB6AP		0x16	/* periph bank 6 access parameters	*/
-#define PB7AP		0x17	/* periph bank 7 access parameters	*/
-#define PBEAR		0x20	/* periph bus error addr reg		*/
-#define PBESR0		0x21	/* periph bus error status reg 0	*/
-#define PBESR1		0x22	/* periph bus error status reg 1	*/
-#define EBC0_CFG	0x23	/* external bus configuration reg	*/
-
-/*
- * GPIO macro register defines
- */
-/* todo: merge with gpio.h header */
-#define GPIO_BASE		GPIO0_BASE
-
-#define GPIO0_OR		(GPIO0_BASE + 0x0)
-#define GPIO0_TCR		(GPIO0_BASE + 0x4)
-#define GPIO0_OSRL		(GPIO0_BASE + 0x8)
-#define GPIO0_OSRH		(GPIO0_BASE + 0xC)
-#define GPIO0_TSRL		(GPIO0_BASE + 0x10)
-#define GPIO0_TSRH		(GPIO0_BASE + 0x14)
-#define GPIO0_ODR		(GPIO0_BASE + 0x18)
-#define GPIO0_IR		(GPIO0_BASE + 0x1C)
-#define GPIO0_RR1		(GPIO0_BASE + 0x20)
-#define GPIO0_RR2		(GPIO0_BASE + 0x24)
-#define GPIO0_RR3		(GPIO0_BASE + 0x28)
-#define GPIO0_ISR1L		(GPIO0_BASE + 0x30)
-#define GPIO0_ISR1H		(GPIO0_BASE + 0x34)
-#define GPIO0_ISR2L		(GPIO0_BASE + 0x38)
-#define GPIO0_ISR2H		(GPIO0_BASE + 0x3C)
-#define GPIO0_ISR3L		(GPIO0_BASE + 0x40)
-#define GPIO0_ISR3H		(GPIO0_BASE + 0x44)
-
-#define GPIO1_OR		(GPIO1_BASE + 0x0)
-#define GPIO1_TCR		(GPIO1_BASE + 0x4)
-#define GPIO1_OSRL		(GPIO1_BASE + 0x8)
-#define GPIO1_OSRH		(GPIO1_BASE + 0xC)
-#define GPIO1_TSRL		(GPIO1_BASE + 0x10)
-#define GPIO1_TSRH		(GPIO1_BASE + 0x14)
-#define GPIO1_ODR		(GPIO1_BASE + 0x18)
-#define GPIO1_IR		(GPIO1_BASE + 0x1C)
-#define GPIO1_RR1		(GPIO1_BASE + 0x20)
-#define GPIO1_RR2		(GPIO1_BASE + 0x24)
-#define GPIO1_RR3		(GPIO1_BASE + 0x28)
-#define GPIO1_ISR1L		(GPIO1_BASE + 0x30)
-#define GPIO1_ISR1H		(GPIO1_BASE + 0x34)
-#define GPIO1_ISR2L		(GPIO1_BASE + 0x38)
-#define GPIO1_ISR2H		(GPIO1_BASE + 0x3C)
-#define GPIO1_ISR3L		(GPIO1_BASE + 0x40)
-#define GPIO1_ISR3H		(GPIO1_BASE + 0x44)
-
-/* General Purpose Timer (GPT) Register Offsets */
-#define GPT0_TBC		0x00000000
-#define GPT0_IM			0x00000018
-#define GPT0_ISS		0x0000001C
-#define GPT0_ISC		0x00000020
-#define GPT0_IE			0x00000024
-#define GPT0_COMP0		0x00000080
-#define GPT0_COMP1		0x00000084
-#define GPT0_COMP2		0x00000088
-#define GPT0_COMP3		0x0000008C
-#define GPT0_COMP4		0x00000090
-#define GPT0_COMP5		0x00000094
-#define GPT0_COMP6		0x00000098
-#define GPT0_MASK0		0x000000C0
-#define GPT0_MASK1		0x000000C4
-#define GPT0_MASK2		0x000000C8
-#define GPT0_MASK3		0x000000CC
-#define GPT0_MASK4		0x000000D0
-#define GPT0_MASK5		0x000000D4
-#define GPT0_MASK6		0x000000D8
-#define GPT0_DCT0		0x00000110
-#define GPT0_DCIS		0x0000011C
-
-#if defined(CONFIG_440)
-#include <asm/ppc440.h>
-#else
-#include <asm/ppc405.h>
-#endif
-
-#include <asm/ppc4xx-sdram.h>
-#include <asm/ppc4xx-ebc.h>
-#if !defined(CONFIG_XILINX_440)
-#include <asm/ppc4xx-uic.h>
-#endif
-
-/*
- * Macro for generating register field mnemonics
- */
-#define	PPC_REG_BITS		32
-#define	PPC_REG_VAL(bit, value)	((value) << ((PPC_REG_BITS - 1) - (bit)))
-
-/*
- * Elide casts when assembling register mnemonics
- */
-#ifndef __ASSEMBLY__
-#define	static_cast(type, val)	(type)(val)
-#else
-#define	static_cast(type, val)	(val)
-#endif
-
-/*
- * Common stuff for 4xx (405 and 440)
- */
-
-#define EXC_OFF_SYS_RESET	0x0100	/* System reset			*/
-#define _START_OFFSET		(EXC_OFF_SYS_RESET + 0x2000)
-
-#define RESET_VECTOR	0xfffffffc
-#define CACHELINE_MASK	(CONFIG_SYS_CACHELINE_SIZE - 1) /* Address mask for
-						cache line aligned data. */
-
-#define CPR0_DCR_BASE	0x0C
-#define CPR0_CFGADDR	(CPR0_DCR_BASE + 0x0)
-#define CPR0_CFGDATA	(CPR0_DCR_BASE + 0x1)
-
-#define SDR_DCR_BASE	0x0E
-#define SDR0_CFGADDR	(SDR_DCR_BASE + 0x0)
-#define SDR0_CFGDATA	(SDR_DCR_BASE + 0x1)
-
-#define SDRAM_DCR_BASE	0x10
-#define SDRAM0_CFGADDR	(SDRAM_DCR_BASE + 0x0)
-#define SDRAM0_CFGDATA	(SDRAM_DCR_BASE + 0x1)
-
-#define EBC_DCR_BASE	0x12
-#define EBC0_CFGADDR	(EBC_DCR_BASE + 0x0)
-#define EBC0_CFGDATA	(EBC_DCR_BASE + 0x1)
-
-/*
- * Macros for indirect DCR access
- */
-#define mtcpr(reg, d)	\
-  do { mtdcr(CPR0_CFGADDR, reg); mtdcr(CPR0_CFGDATA, d); } while (0)
-#define mfcpr(reg, d)	\
-  do { mtdcr(CPR0_CFGADDR, reg); d = mfdcr(CPR0_CFGDATA); } while (0)
-
-#define mtebc(reg, d)	\
-  do { mtdcr(EBC0_CFGADDR, reg); mtdcr(EBC0_CFGDATA, d); } while (0)
-#define mfebc(reg, d)	\
-  do { mtdcr(EBC0_CFGADDR, reg); d = mfdcr(EBC0_CFGDATA); } while (0)
-
-#define mtsdram(reg, d)	\
-  do { mtdcr(SDRAM0_CFGADDR, reg); mtdcr(SDRAM0_CFGDATA, d); } while (0)
-#define mfsdram(reg, d)	\
-  do { mtdcr(SDRAM0_CFGADDR, reg); d = mfdcr(SDRAM0_CFGDATA); } while (0)
-
-#define mtsdr(reg, d)	\
-  do { mtdcr(SDR0_CFGADDR, reg); mtdcr(SDR0_CFGDATA, d); } while (0)
-#define mfsdr(reg, d)	\
-  do { mtdcr(SDR0_CFGADDR, reg); d = mfdcr(SDR0_CFGDATA); } while (0)
-
-#ifndef __ASSEMBLY__
-
-typedef struct
-{
-	unsigned long freqDDR;
-	unsigned long freqEBC;
-	unsigned long freqOPB;
-	unsigned long freqPCI;
-	unsigned long freqPLB;
-	unsigned long freqTmrClk;
-	unsigned long freqUART;
-	unsigned long freqProcessor;
-	unsigned long freqVCOHz;
-	unsigned long freqVCOMhz;	/* in MHz                          */
-	unsigned long pciClkSync;	/* PCI clock is synchronous        */
-	unsigned long pciIntArbEn;	/* Internal PCI arbiter is enabled */
-	unsigned long pllExtBusDiv;
-	unsigned long pllFbkDiv;
-	unsigned long pllFwdDiv;
-	unsigned long pllFwdDivA;
-	unsigned long pllFwdDivB;
-	unsigned long pllOpbDiv;
-	unsigned long pllPciDiv;
-	unsigned long pllPlbDiv;
-} PPC4xx_SYS_INFO;
-
-static inline u32 get_mcsr(void)
-{
-	u32 val;
-
-	asm volatile("mfspr %0, 0x23c" : "=r" (val) :);
-	return val;
-}
-
-static inline void set_mcsr(u32 val)
-{
-	asm volatile("mtspr 0x23c, %0" : "=r" (val) :);
-}
-
-int ppc4xx_pci_sync_clock_config(u32 async);
-
-unsigned long get_OPB_freq(void);
-unsigned long get_PCI_freq(void);
-
-typedef PPC4xx_SYS_INFO sys_info_t;
-int ppc440spe_revB(void);
-void get_sys_info(sys_info_t *);
-
-#endif	/* __ASSEMBLY__ */
-
-/* for multi-cpu support */
-#define NA_OR_UNKNOWN_CPU	-1
-
-#endif	/* __PPC4XX_H__ */
diff --git a/arch/powerpc/include/asm/ppc4xx_config.h b/arch/powerpc/include/asm/ppc4xx_config.h
deleted file mode 100644
index f38fde5..0000000
--- a/arch/powerpc/include/asm/ppc4xx_config.h
+++ /dev/null
@@ -1,25 +0,0 @@
-/*
- * (C) Copyright 2008-2009
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * (C) Copyright 2009
- * Dirk Eibach,  Guntermann & Drunck GmbH, eibach@gdsys.de
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef __PPC4xx_CONFIG_H
-#define __PPC4xx_CONFIG_H
-
-#include <common.h>
-
-struct ppc4xx_config {
-	char label[16];
-	char description[64];
-	u8 val[CONFIG_4xx_CONFIG_BLOCKSIZE];
-};
-
-extern struct ppc4xx_config ppc4xx_config_val[];
-extern int ppc4xx_config_count;
-
-#endif /* __PPC4xx_CONFIG_H */
diff --git a/arch/powerpc/include/asm/processor.h b/arch/powerpc/include/asm/processor.h
index 6549a09..30ac4f8 100644
--- a/arch/powerpc/include/asm/processor.h
+++ b/arch/powerpc/include/asm/processor.h
@@ -89,11 +89,6 @@
 
 /* Special Purpose Registers (SPRNs)*/
 
-/* PPC440 Architecture is BOOK-E */
-#ifdef CONFIG_440
-#define CONFIG_BOOKE
-#endif
-
 #define SPRN_CCR0	0x3B3	/* Core Configuration Register 0 */
 #ifdef CONFIG_BOOKE
 #define SPRN_CCR1	0x378	/* Core Configuration Register for 440 only */
@@ -570,12 +565,7 @@
 #define SPRN_MCAR	0x23d	/* Machine Check Address register */
 #define MCSR_MCS	0x80000000	/* Machine Check Summary */
 #define MCSR_IB		0x40000000	/* Instruction PLB Error */
-#if defined(CONFIG_440)
-#define MCSR_DRB	0x20000000	/* Data Read PLB Error */
-#define MCSR_DWB	0x10000000	/* Data Write PLB Error */
-#else
 #define MCSR_DB		0x20000000	/* Data PLB Error */
-#endif /* defined(CONFIG_440) */
 #define MCSR_TLBP	0x08000000	/* TLB Parity Error */
 #define MCSR_ICP	0x04000000	/* I-Cache Parity Error */
 #define MCSR_DCSP	0x02000000	/* D-Cache Search Parity Error */
@@ -764,7 +754,7 @@
 #define MAS7	SPRN_MAS7
 #define MAS8 	SPRN_MAS8
 
-#if defined(CONFIG_4xx) || defined(CONFIG_44x) || defined(CONFIG_MPC85xx)
+#if defined(CONFIG_MPC85xx)
 #define DAR_DEAR DEAR
 #else
 #define DAR_DEAR DAR
@@ -1369,7 +1359,7 @@
 #endif
 #endif /* CONFIG_MACH_SPECIFIC */
 
-#if defined(CONFIG_MPC85xx) || defined(CONFIG_440)
+#if defined(CONFIG_MPC85xx)
  #define EPAPR_MAGIC	(0x45504150)
 #else
  #define EPAPR_MAGIC	(0x65504150)